From da541327d2ecfc9043205a7bd81c0ed71c4313fa Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Mon, 16 May 2022 16:21:51 +0200 Subject: soc/intel/elkhartlake: Enable SMBus depending on dev state Program the `SmbusEnable` FSP UPD according to the SMBus PCI device's state in the devicetree. This avoids having to manually make sure the SMBus PCI device and the `SmbusEnable` setting are in sync. Change-Id: I275a981f914a55dc57a75e7d436912ff0255a293 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/64402 Reviewed-by: Lean Sheng Tan Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/intel/elkhartlake_crb/variants') diff --git a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb index 0fdc88a7a8..baf0ba12ee 100644 --- a/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb +++ b/src/mainboard/intel/elkhartlake_crb/variants/ehlcrb/devicetree.cb @@ -14,7 +14,6 @@ chip soc/intel/elkhartlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" register "Heci2Enable" = "1" # Display related UPDs -- cgit v1.2.3