From d2afd87b0dd438d9e322c867b48f6052957370c0 Mon Sep 17 00:00:00 2001 From: "Tan, Lean Sheng" Date: Wed, 18 Nov 2020 04:37:59 -0800 Subject: mb/intel/ehlcrb: Add initial mainboard code This is a initial mainboard code cloned entirely from jasperlake_rvp aimed to serve as base for further mainboard check-ins. This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/37868 List of changes on top off initial jasperlake_rvp clone: 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jslrvp" with "ehlcrb" 4. Remove unwanted SPD file, add empty SPD as placeholder 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config 7. Empty GPIO configurations, to be filled as per board 8. Empty memory.c configurations, to be filled as per board 9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB 10. Replace jslrvp variant with ehlcrb variant Changes to follow on top of this: 1. Add correct memory parameters, add SPDs 2. Clean up devicetree as per tigerlake SOC 3. Add GPIO support 4. Update ehl fmd file to replace 32MB chromeos.fmd Signed-off-by: Tan, Lean Sheng Change-Id: I2cbe9f12468318680b148739edec5222582e42a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/mainboard/intel/elkhartlake_crb/board_id.c | 43 ++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) create mode 100644 src/mainboard/intel/elkhartlake_crb/board_id.c (limited to 'src/mainboard/intel/elkhartlake_crb/board_id.c') diff --git a/src/mainboard/intel/elkhartlake_crb/board_id.c b/src/mainboard/intel/elkhartlake_crb/board_id.c new file mode 100644 index 0000000000..90609ff079 --- /dev/null +++ b/src/mainboard/intel/elkhartlake_crb/board_id.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "board_id.h" + +static uint32_t get_board_id_via_ext_ec(void) +{ + uint32_t id = BOARD_ID_INIT; + + if (google_chromeec_get_board_version(&id)) + id = BOARD_ID_UNKNOWN; + + return id; +} + +/* + * Get Board ID via EC I/O port write/read + * Board id is 5 bit, so mask other bits while returning board id. + */ +int get_board_id(void) +{ + MAYBE_STATIC_NONZERO int id = -1; + + if (id < 0) { + if (CONFIG(EC_GOOGLE_CHROMEEC)) { + id = get_board_id_via_ext_ec(); + } else { + uint8_t buffer[2]; + uint8_t index; + if (send_ec_command(EC_FAB_ID_CMD) == 0) { + for (index = 0; index < sizeof(buffer); index++) + buffer[index] = recv_ec_data(); + id = (buffer[0] << 8) | buffer[1]; + } + } + } + + return (id & 0x1f); +} -- cgit v1.2.3