From e4188a23dde8db7f1386f3f782b8a43c40811119 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 7 Sep 2017 17:05:57 +0200 Subject: mb/intel/dg43gt: Configure clockgen MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This makes the VGA output on the DVI-I connector usable. This reuses vendor settings. Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21440 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/intel/dg43gt/Kconfig | 1 + src/mainboard/intel/dg43gt/devicetree.cb | 14 +++++++++++++- 2 files changed, 14 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/dg43gt') diff --git a/src/mainboard/intel/dg43gt/Kconfig b/src/mainboard/intel/dg43gt/Kconfig index d55f82dea5..b299f42e1f 100644 --- a/src/mainboard/intel/dg43gt/Kconfig +++ b/src/mainboard/intel/dg43gt/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select INTEL_EDID select MAINBOARD_HAS_NATIVE_VGA_INIT + select DRIVERS_I2C_CK505 config VGA_BIOS_ID string diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index 6421673825..79a8eb7309 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -101,7 +101,19 @@ chip northbridge/intel/x4x # Northbridge end device pci 1f.1 on end # PATA/IDE device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMbus + device pci 1f.3 on # SMbus + chip drivers/i2c/ck505 # SLG8XP549T + register "mask" = "{ 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff }" + register "regs" = "{ 0x11, 0xd9, 0xff, + 0xfd, 0xff, 0x00, 0x00, + 0x06, 0x10, 0x05, 0x01, + 0x80, 0x0d }" + device i2c 69 on end + end + end device pci 1f.4 off end device pci 1f.5 on end # IDE device pci 1f.6 off end -- cgit v1.2.3