From 92ce1fb45eda81d8667db63ec8eb649ed87c743c Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 7 Sep 2017 18:15:28 +0200 Subject: mb/intel/dg43gt: Fix smbus IRQ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This board uses the reset defaults for DxxIP and DxxIR. The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family" mistakenly says in the D31IP register that all function have INTB as default. This is however not true as documented in the reset default value. This fixes the DSDT such that the SMBus device gets a route for the INT C interrupt it uses. Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/21442 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/intel/dg43gt') diff --git a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl index 510af9abb6..8e56679f40 100644 --- a/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl +++ b/src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl @@ -52,6 +52,8 @@ Method(_PRT) Package() { 0x001dffff, 3, 0, 0x13 }, /* SMBUS/SATA/PATA 0:1f.2, 0:1f.3 */ Package() { 0x001fffff, 1, 0, 0x11 }, + Package() { 0x001fffff, 2, 0, 0x12 }, + Package() { 0x001fffff, 3, 0, 0x13 }, }) } Else { Return (Package() { @@ -86,6 +88,8 @@ Method(_PRT) Package() { 0x001dffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, /* PATA/SATA/SMBUS 0:1f.1-3 */ Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, + Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, }) } } -- cgit v1.2.3