From fecf77770b8e68b9ef82021ca53c31db93736d93 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Sat, 9 Nov 2019 14:19:04 +0100
Subject: sb/intel/i82801gx: Add common LPC decode code

Generic LPC decode ranges can now be set from the devicetree.

Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/intel/dg41wv/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard/intel/dg41wv/devicetree.cb')

diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb
index 295fbc4f38..c00e998bcc 100644
--- a/src/mainboard/intel/dg41wv/devicetree.cb
+++ b/src/mainboard/intel/dg41wv/devicetree.cb
@@ -65,6 +65,8 @@ chip northbridge/intel/x4x		# Northbridge
 			register "ide_enable_primary" = "0x1"
 			register "gpe0_en" = "0x440"
 
+			register "gen1_dec" = "0x00fc0a01" # HWM
+
 			device pci 1b.0 on		# Audio
 				subsystemid 0x8086 0x5756
 			end
-- 
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