From d28d5071906e15c88939d889fbe40b117f5c303b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 16 Jun 2019 23:36:28 +0200 Subject: sb/intel/bd82x6x/lpc: Set up default LPC decode ranges This sets up some common default LPC decode ranges in a common place. This may set up more decode ranges than needed but that typically does not hurt. Mainboards needing additional ranges can do so in the mainboard pch_enable_lpc hook. Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/intel/dcp847ske/early_southbridge.c | 10 ---------- 1 file changed, 10 deletions(-) (limited to 'src/mainboard/intel/dcp847ske') diff --git a/src/mainboard/intel/dcp847ske/early_southbridge.c b/src/mainboard/intel/dcp847ske/early_southbridge.c index 705ace9bc6..984629574c 100644 --- a/src/mainboard/intel/dcp847ske/early_southbridge.c +++ b/src/mainboard/intel/dcp847ske/early_southbridge.c @@ -27,18 +27,8 @@ #include "superio.h" #include "thermal.h" -#if CONFIG(DISABLE_UART_ON_TESTPADS) -#define DEBUG_UART_EN 0 -#else -#define DEBUG_UART_EN COMA_LPC_EN -#endif - void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, - CNF2_LPC_EN | DEBUG_UART_EN); - /* Decode SuperIO 0x0a00 */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), LPC_GEN1_DEC, 0x00fc0a01); } void mainboard_rcba_config(void) -- cgit v1.2.3