From 7a9520483aad833cb11fadf3ee12decee8d1e521 Mon Sep 17 00:00:00 2001 From: Tobias Diedrich Date: Sun, 3 Dec 2017 10:09:28 +0100 Subject: intel/dcp847ske: Add Intel NUC DCP847SKE https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE Created using autoport and manual edits. mainboard_fill_pei_data copied and adjusted from samsung/lumpy. Tested: - RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V). - RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V). - SeaBIOS stable payload. - Linux 4.13.14 payload. - Booting into Linux 4.13.14 with Debian/unstable installed on the internal mSATA slot. - Non-native raminit (works). - Native raminit - KVR1333D3S9 doesn't work. - KVR16LS11 only works at 1.5V. - Native VGA init, HDMI port detection with libgfxinit. - Basic ACPI functions (power button event; power-off; reboot). - Suspend to RAM and resume works. - PCIe WLAN in half-minicard slot. - USB device in half-minicard slot. - PCIe device in full-minicard slot. - mSATA device in full-minicard slot. - Fan spins up/down in response to CPU load. Known issues: - Native raminit fails timC calibration with the RAM I have. - Technical Product Specification mentions overcurrent protection for back panel and front panel USB connectors, but I haven't been able to trigger it with either native fw or coreboot (tried up to 2.5A load). Untested: - USB debug port. Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90 Signed-off-by: Tobias Diedrich Reviewed-on: https://review.coreboot.org/22683 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Arthur Heymans --- src/mainboard/intel/dcp847ske/thermal.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) create mode 100644 src/mainboard/intel/dcp847ske/thermal.h (limited to 'src/mainboard/intel/dcp847ske/thermal.h') diff --git a/src/mainboard/intel/dcp847ske/thermal.h b/src/mainboard/intel/dcp847ske/thermal.h new file mode 100644 index 0000000000..914b3232a4 --- /dev/null +++ b/src/mainboard/intel/dcp847ske/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * Copyright (C) 2017 Tobias Diedrich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef DCP847SKE_THERMAL_H +#define DPC847SKE_THERMAL_H + +/* TODO: These should be generated at runtime from + * MSR_TEMPERATURE_TARGET (0x1a2) */ + +/* Temperature which OS will shutdown at (Tjmax) */ +#define CRITICAL_TEMPERATURE 100 + +/* Temperature which OS will throttle CPU (Tcontrol) */ +#define PASSIVE_TEMPERATURE 86 + +#endif -- cgit v1.2.3