From 7a9520483aad833cb11fadf3ee12decee8d1e521 Mon Sep 17 00:00:00 2001
From: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Date: Sun, 3 Dec 2017 10:09:28 +0100
Subject: intel/dcp847ske: Add Intel NUC DCP847SKE

https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE

Created using autoport and manual edits.
mainboard_fill_pei_data copied and adjusted from samsung/lumpy.

Tested:
- RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V).
- RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V).
- SeaBIOS stable payload.
- Linux 4.13.14 payload.
- Booting into Linux 4.13.14 with Debian/unstable installed on the
  internal mSATA slot.
- Non-native raminit (works).
- Native raminit
  - KVR1333D3S9 doesn't work.
  - KVR16LS11 only works at 1.5V.
- Native VGA init, HDMI port detection with libgfxinit.
- Basic ACPI functions (power button event; power-off; reboot).
- Suspend to RAM and resume works.
- PCIe WLAN in half-minicard slot.
- USB device in half-minicard slot.
- PCIe device in full-minicard slot.
- mSATA device in full-minicard slot.
- Fan spins up/down in response to CPU load.

Known issues:
- Native raminit fails timC calibration with the RAM I have.
- Technical Product Specification mentions overcurrent protection
  for back panel and front panel USB connectors, but I haven't
  been able to trigger it with either native fw or coreboot
  (tried up to 2.5A load).

Untested:
- USB debug port.

Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
---
 src/mainboard/intel/dcp847ske/dsdt.asl | 43 ++++++++++++++++++++++++++++++++++
 1 file changed, 43 insertions(+)
 create mode 100644 src/mainboard/intel/dcp847ske/dsdt.asl

(limited to 'src/mainboard/intel/dcp847ske/dsdt.asl')

diff --git a/src/mainboard/intel/dcp847ske/dsdt.asl b/src/mainboard/intel/dcp847ske/dsdt.asl
new file mode 100644
index 0000000000..f637648a28
--- /dev/null
+++ b/src/mainboard/intel/dcp847ske/dsdt.asl
@@ -0,0 +1,43 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot@tdiedrich.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x03,		// DSDT revision: ACPI v3.0
+	"COREv4",	// OEM id
+	"COREBOOT",	// OEM table id
+	0x20141018	// OEM revision
+)
+{
+	// Some generic macros
+	#include "acpi/platform.asl"
+	#include <cpu/intel/model_206ax/acpi/cpu.asl>
+	#include <southbridge/intel/bd82x6x/acpi/platform.asl>
+	/* global NVS and variables.  */
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+		#include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl>
+		}
+	}
+}
-- 
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