From dc584c3f221bb59ee6b89e5517617b9d1d74bcf3 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 12 Nov 2019 20:37:21 +0100
Subject: nb/intel/i945: Move boilerplate romstage to a common location

This adds callbacks for mainboard specific init.

Change-Id: Ib67bc492a7b7f02f9b57a52fd6730e16501b436e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36787
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/d945gclf/romstage.c | 52 ++-------------------------------
 1 file changed, 2 insertions(+), 50 deletions(-)

(limited to 'src/mainboard/intel/d945gclf')

diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index ada6e61c00..7a8f5d1656 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -13,22 +13,14 @@
  * GNU General Public License for more details.
  */
 
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ops.h>
-#include <cpu/x86/lapic.h>
 #include <superio/smsc/lpc47m15x/lpc47m15x.h>
-#include <console/console.h>
-#include <arch/romstage.h>
 #include <northbridge/intel/i945/i945.h>
-#include <northbridge/intel/i945/raminit.h>
 #include <southbridge/intel/i82801gx/i82801gx.h>
-#include <southbridge/intel/common/pmclib.h>
 
 #define SERIAL_DEV PNP_DEV(0x2e, LPC47M15X_SP1)
 #define PME_DEV PNP_DEV(0x2e, LPC47M15X_PME)
 
-static void rcba_config(void)
+void mainboard_late_rcba_config(void)
 {
 	/* Set up virtual channel 0 */
 	//RCBA32(0x0014) = 0x80000001;
@@ -47,49 +39,9 @@ static void rcba_config(void)
 	// RCBA32(0x341c) = 0x00000001;
 }
 
-void mainboard_romstage_entry(void)
+void mainboard_superio_config(void)
 {
-	int s3resume = 0, boot_mode = 0;
-
-	enable_lapic();
-
-	i82801gx_lpc_setup();
 	/* Enable SuperIO PM */
 	lpc47m15x_enable_serial(PME_DEV, 0x680);
 	lpc47m15x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); /* 0x3f8 */
-
-	/* Set up the console */
-	console_init();
-
-	if (MCHBAR16(SSKPD) == 0xCAFE) {
-		printk(BIOS_DEBUG, "soft reset detected.\n");
-		boot_mode = 1;
-	}
-
-	/* Perform some early chipset initialization required
-	 * before RAM initialization can work
-	 */
-	i82801gx_early_init();
-	i945_early_initialization();
-
-	s3resume = southbridge_detect_s3_resume();
-
-	/* Enable SPD ROMs and DDR-II DRAM */
-	enable_smbus();
-
-	if (CONFIG(DEBUG_RAM_SETUP))
-		dump_spd_registers();
-
-	sdram_initialize(s3resume ? 2 : boot_mode, NULL);
-
-	/* This should probably go away. Until now it is required
-	 * and mainboard specific
-	 */
-	rcba_config();
-
-	/* Chipset Errata! */
-	fixup_i945_errata();
-
-	/* Initialize the internal PCIe links before we go into stage2 */
-	i945_late_initialization(s3resume);
 }
-- 
cgit v1.2.3