From 408d3928236f275633f8656cc12e32949d304d9f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Fri, 17 Jun 2016 10:43:48 +0300
Subject: intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP
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Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15228
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/intel/d510mo/romstage.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/mainboard/intel/d510mo')

diff --git a/src/mainboard/intel/d510mo/romstage.c b/src/mainboard/intel/d510mo/romstage.c
index 28481c026f..f73bf649a9 100644
--- a/src/mainboard/intel/d510mo/romstage.c
+++ b/src/mainboard/intel/d510mo/romstage.c
@@ -24,6 +24,7 @@
 #include <northbridge/intel/pineview/raminit.h>
 #include <northbridge/intel/pineview/pineview.h>
 #include <cpu/x86/bist.h>
+#include <cpu/intel/romstage.h>
 #include <cpu/x86/lapic.h>
 #include <superio/winbond/w83627thg/w83627thg.h>
 #include <superio/winbond/common/winbond.h>
@@ -33,7 +34,6 @@
 #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
 #define SUPERIO_DEV PNP_DEV(0x4e, 0)
 
-#include <cpu/intel/romstage.h>
 
 /* Early mainboard specific GPIO setup */
 static void mb_gpio_init(void)
@@ -102,7 +102,7 @@ static void rcba_config(void)
 	RCBA32(0x3418) |= 1;
 }
 
-void main(unsigned long bist)
+void mainboard_romstage_entry(unsigned long bist)
 {
 	const u8 spd_addrmap[4] = { 0x50, 0x51, 0, 0 };
 
-- 
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