From 79a7ad6dda8a5a4272b6a59cef750af2f2585dc2 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Jan 2019 15:33:46 +0100 Subject: mb/{d41s,d510mo}: Remove references to PCIe port 5 and 6 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The southbridge has the function disable bits for port 5 and 6 strapped RO to 1 (disable). Change-Id: I2948935d42b9031d61f9e5b3f06b769e68f5a042 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30712 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/intel/d510mo/devicetree.cb | 1 - 1 file changed, 1 deletion(-) (limited to 'src/mainboard/intel/d510mo/devicetree.cb') diff --git a/src/mainboard/intel/d510mo/devicetree.cb b/src/mainboard/intel/d510mo/devicetree.cb index a80180a32e..a00861043e 100644 --- a/src/mainboard/intel/d510mo/devicetree.cb +++ b/src/mainboard/intel/d510mo/devicetree.cb @@ -49,7 +49,6 @@ chip northbridge/intel/pineview # Northbridge device pci 1c.1 on end # PCIe 2 device pci 1c.2 on end # PCIe 3 device pci 1c.3 on end # PCIe 4 - # (PCIe 5 and 6 not on nm10?) device pci 1d.0 on end # USB device pci 1d.1 on end # USB device pci 1d.2 on end # USB -- cgit v1.2.3