From ec505ad21c923c114a16b2710a0113f657765430 Mon Sep 17 00:00:00 2001 From: "Jonathan A. Kollasch" Date: Tue, 7 Jul 2015 12:57:46 -0500 Subject: azalia: fix up and clean up shrinkage of boilerplate code Should fix regression in HDA verb setup on nvidia mcp55 and intel sch southbridges. The mcp55 code could not find the mainboard's verb table because the table was not even being compiled in. The sch boards appeared to have the same issue. Intel broadwell and fsp_bd82x6x seemed to have not gotten the boilerplate shrink, so apply it to those too. Followup-to: Ib3e09644c0ee71aacb067adaa85653d151b52078 (azalia: Shrink boilerplate) Change-Id: If7aae69f5171db67055ffe220bdff392caaa5d9f Signed-off-by: Jonathan A. Kollasch Reviewed-on: http://review.coreboot.org/10826 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/cougar_canyon2/hda_verb.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/intel/cougar_canyon2') diff --git a/src/mainboard/intel/cougar_canyon2/hda_verb.c b/src/mainboard/intel/cougar_canyon2/hda_verb.c index 51b635696e..a110246622 100644 --- a/src/mainboard/intel/cougar_canyon2/hda_verb.c +++ b/src/mainboard/intel/cougar_canyon2/hda_verb.c @@ -37,4 +37,7 @@ const u32 cim_verb_data[] = { /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ AZALIA_PIN_CFG(0x3, 0x07, 0x18560030) }; + +const u32 pc_beep_verbs[0] = {}; + AZALIA_ARRAY_SIZES; -- cgit v1.2.3