From 45022ae056cdbf58429b77daf2da176306312801 Mon Sep 17 00:00:00 2001
From: Patrick Rudolph <siro@das-labor.org>
Date: Mon, 1 Oct 2018 19:17:11 +0200
Subject: intel: Use CF9 reset (part 1)

Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.

Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/mainboard/intel/cougar_canyon2/romstage.c | 10 ++--------
 1 file changed, 2 insertions(+), 8 deletions(-)

(limited to 'src/mainboard/intel/cougar_canyon2')

diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index 9d3b478f2f..38af2b881b 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -21,6 +21,7 @@
 #include <lib.h>
 #include <timestamp.h>
 #include <arch/io.h>
+#include <cf9_reset.h>
 #include <device/pci_def.h>
 #include <device/pnp_def.h>
 #include <cpu/x86/lapic.h>
@@ -28,7 +29,6 @@
 #include <console/console.h>
 #include <halt.h>
 #include <program_loading.h>
-#include <reset.h>
 #include <superio/smsc/sio1007/chip.h>
 #include <fsp_util.h>
 #include <northbridge/intel/fsp_sandybridge/northbridge.h>
@@ -41,12 +41,6 @@
 
 #define SIO_PORT 0x164e
 
-static inline void reset_system(void)
-{
-	hard_reset();
-	halt();
-}
-
 static void pch_enable_lpc(void)
 {
 	pci_devfn_t dev = PCH_LPC_DEV;
@@ -292,7 +286,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
 	cbmem_was_initted = !cbmem_recovery(0);
 
 	if(cbmem_was_initted) {
-		reset_system();
+		system_reset();
 	}
 
 	/* Save the HOB pointer in CBMEM to be used in ramstage. */
-- 
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