From 2dd3f877cc7926f5ac1cfd5a7e5d546c8be2121c Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Fri, 25 Apr 2014 15:09:27 -0600 Subject: cougar_canyon2: Switch CPU/NB/SB to the shared FSP code CPU - fsp_model_206ax: - Remove Kconfig options and mark this as using the FSP. - Use shared FSP cache_as_ram.inc file Mainboard - intel/cougar_canyon2: - Update to use the shared FSP header file. - Modify to call copy_and_run() directly instead of returning to cache_as_ram.inc. Northbridge - fsp_sandybridge: - remove mrccache, fsp_util.[ch] - add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits. - Update to use the shared FSP header file. These changes were validated with FSP: CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801 MD5: 24965382fbb832f7b184d3f24157abda Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4 Signed-off-by: Martin Roth Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/5636 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/mainboard/intel/cougar_canyon2/romstage.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) (limited to 'src/mainboard/intel/cougar_canyon2') diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index afd7e25655..69389257d2 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -33,7 +33,7 @@ #include #include #include "superio/smsc/sio1007/chip.h" -#include "northbridge/intel/fsp_sandybridge/fsp_util.h" +#include #include "northbridge/intel/fsp_sandybridge/northbridge.h" #include "northbridge/intel/fsp_sandybridge/raminit.h" #include "southbridge/intel/fsp_bd82x6x/pch.h" @@ -42,6 +42,7 @@ #include #include #include "gpio.h" +#include static inline void reset_system(void) { @@ -345,13 +346,9 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { cbmemc_reinit(); #endif -/* - * FSP returns to this function instead of main, so we can't return back - * to the cache_as_ram.inc. Just jump there to finish the ramstage loading. - */ - asm volatile ( - "jmp romstage_main_return\n" - ); + /* Load the ramstage. */ + copy_and_run(); + while (1); } void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -- cgit v1.2.3