From 32ca3ac9abba771213a180699e07132e8558ce37 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 17 Jul 2021 04:58:16 +0200 Subject: mb/intel/coffeelake_rvp: Use CHIPSET_LOCKDOWN_COREBOOT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, internal flashing is not possible due to FSP lockdown. Thus let coreboot do chipset lockdown on all variants. Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407 Reviewed-by: Lean Sheng Tan Reviewed-by: Angel Pons Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/intel/coffeelake_rvp/variants/baseboard') diff --git a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb index 12b1c47f33..49c400f457 100644 --- a/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb +++ b/src/mainboard/intel/coffeelake_rvp/variants/baseboard/devicetree.cb @@ -1,5 +1,7 @@ chip soc/intel/cannonlake + register "common_soc_config.chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT" + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3