From dfc9917080a9175fef2c40288c586ff9dd5861f3 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Tue, 7 Aug 2018 12:06:23 +0530 Subject: mb/intel/coffeelake_rvp: Add support for new board coffeelake RVP Add support for new board coffeelake RVP. This patch is a copy patch and copies entire coffeelake_rvp folder from cannonlake_rvp. Changes done on top of copy: 1. Change copyright year from 2017 to 2018 2. Rename Cannonlake to Coffelake whenever applicable 3. Update entries in Kconfig and Kconfig.name 4. Rename variant directories to match coffeelake boards Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/27904 Reviewed-by: Arthur Heymans Reviewed-by: Naresh Solanki Reviewed-by: Lijian Zhao Tested-by: build bot (Jenkins) --- src/mainboard/intel/coffeelake_rvp/mainboard.c | 68 ++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 src/mainboard/intel/coffeelake_rvp/mainboard.c (limited to 'src/mainboard/intel/coffeelake_rvp/mainboard.c') diff --git a/src/mainboard/intel/coffeelake_rvp/mainboard.c b/src/mainboard/intel/coffeelake_rvp/mainboard.c new file mode 100644 index 0000000000..522cfc426b --- /dev/null +++ b/src/mainboard/intel/coffeelake_rvp/mainboard.c @@ -0,0 +1,68 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +static void mainboard_init(void *chip_info) +{ + const struct pad_config *pads; + size_t num; + + pads = variant_gpio_table(&num); + gpio_configure_pads(pads, num); +} + +static unsigned long mainboard_write_acpi_tables(struct device *device, + unsigned long current, + acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + variant_nhlt_init(nhlt); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; + dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mainboard_enable, +}; -- cgit v1.2.3