From 7b2b57b0b8ae451f80b97582cc6c86004aaab471 Mon Sep 17 00:00:00 2001
From: Shuo Liu <shuo.liu@intel.com>
Date: Mon, 22 Apr 2024 04:31:41 +0800
Subject: soc/intel/xeon_sp/acpi: Refactor Xeon-SP ASL file location

soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX
platforms and not forward compatible to later SoC generations.
Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance.

TEST=Build and boot on intel/archercity CRB

Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/intel/cedarisland_crb/dsdt.asl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'src/mainboard/intel/cedarisland_crb/dsdt.asl')

diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl
index 3d8321793c..59ce66c8d7 100644
--- a/src/mainboard/intel/cedarisland_crb/dsdt.asl
+++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl
@@ -22,7 +22,7 @@ DefinitionBlock(
 	{
 		Device (PCI0)
 		{
-			#include <soc/intel/xeon_sp/acpi/southcluster.asl>
+			#include <soc/intel/xeon_sp/acpi/gen1/southcluster.asl>
 			#include <soc/intel/common/block/acpi/acpi/lpc.asl>
 
 		}
-- 
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