From 1b325dd971c84d75aa5a53405c11e0ad8f2517b9 Mon Sep 17 00:00:00 2001 From: Andrey Petrov Date: Fri, 20 Mar 2020 12:12:12 -0700 Subject: mb/intel/cedarisland_crb: Add Cedar Island CRB Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Andrey Petrov Change-Id: Ie2f944964e938d8026a6d5d8a22a8449199d08aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/39714 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov Reviewed-by: Angel Pons --- src/mainboard/intel/cedarisland_crb/dsdt.asl | 59 ++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 src/mainboard/intel/cedarisland_crb/dsdt.asl (limited to 'src/mainboard/intel/cedarisland_crb/dsdt.asl') diff --git a/src/mainboard/intel/cedarisland_crb/dsdt.asl b/src/mainboard/intel/cedarisland_crb/dsdt.asl new file mode 100644 index 0000000000..3dc45d5f2c --- /dev/null +++ b/src/mainboard/intel/cedarisland_crb/dsdt.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ + +#include +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include + #include + + } + + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + } + } + +} -- cgit v1.2.3