From 04a2edf689f79ffeb540c3e39e8893e75d5efd7a Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sun, 26 Apr 2020 21:08:20 +0300 Subject: mb/intel/cedarisland_crb: use common driver to configure GPIO According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with vendors firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file cedarisland/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I90b91e6dbf8c65c747d0e0d94c61023e610f93ab Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/40734 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov --- src/mainboard/intel/cedarisland_crb/bootblock.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/mainboard/intel/cedarisland_crb/bootblock.c') diff --git a/src/mainboard/intel/cedarisland_crb/bootblock.c b/src/mainboard/intel/cedarisland_crb/bootblock.c index ea82ecc73f..3be0f8bc10 100644 --- a/src/mainboard/intel/cedarisland_crb/bootblock.c +++ b/src/mainboard/intel/cedarisland_crb/bootblock.c @@ -10,9 +10,13 @@ #include #include #include +#include "include/gpio.h" void bootblock_mainboard_early_init(void) { + /* Configure Lewisburg PCH GPIOs */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + /* Enable COM1 only */ pcr_write32(PID_DMI, 0x2770, 0); pcr_write32(PID_DMI, 0x2774, 1); -- cgit v1.2.3