From a64b4f454894988a9c043d53d00b493852f261a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 15 Oct 2020 00:36:29 +0200 Subject: mb/*,soc/intel: drop the obsolete dt option `speed_shift_enable` MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The dt option `speed_shift_enable` is obsolete now. Drop it. Change-Id: I5ac3b8efe37aedd442962234478fcdce675bf105 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46462 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Frans Hendriks --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 3 --- src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 3 --- 2 files changed, 6 deletions(-) (limited to 'src/mainboard/intel/cannonlake_rvp') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index e10059887e..1110bc1e32 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -60,9 +60,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index bf7aa1e962..42023149a9 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -57,9 +57,6 @@ chip soc/intel/cannonlake register "PcieClkSrcClkReq[4]" = "4" register "PcieClkSrcClkReq[5]" = "5" - # Enable "Intel Speed Shift Technology" - register "speed_shift_enable" = "1" - # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" -- cgit v1.2.3