From 8cf149007fb0802125fa7b90025a10d4c365d426 Mon Sep 17 00:00:00 2001 From: Vaibhav Shankar Date: Mon, 19 Mar 2018 19:04:16 -0700 Subject: mainboard/intel/cannonlake_rvp: Enable S0ix This patch enables S0ix from the devicetree. Change-Id: I38662dc7203366bdee5f1c7aaa18979867a79ba1 Signed-off-by: Vaibhav Shankar Reviewed-on: https://review.coreboot.org/25293 Reviewed-by: Sumeet R Pawnikar Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 3 +++ src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 3 +++ 2 files changed, 6 insertions(+) (limited to 'src/mainboard/intel/cannonlake_rvp') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 3e60ed946b..18aa65d890 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -70,6 +70,9 @@ chip soc/intel/cannonlake # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" + # Enable S0ix + register "s0ix_enable" = "1" + # Audio register "i2c[3]" = "{ .speed = I2C_SPEED_STANDARD, diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 8502048880..6dd1893948 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -68,6 +68,9 @@ chip soc/intel/cannonlake # GPIO for SD card detect register "sdcard_cd_gpio" = "GPP_G5" + # Enable S0ix + register "s0ix_enable" = "1" + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- cgit v1.2.3