From 584af87483899f49f30039aa7d5861a50ce73612 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Wed, 4 Oct 2017 18:19:14 -0700 Subject: intel/cannonlake_rvp: Enable Audio DSP Enable Audio DSP by default on cannonlake rvp platform. TEST=Boot up into OS and check Audio driver debug print. Change-Id: I6892c6d349019550c967ef30b84d385f396fc388 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21888 Tested-by: build bot (Jenkins) Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Aaron Durbin --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 3 +++ src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 3 +++ 2 files changed, 6 insertions(+) (limited to 'src/mainboard/intel/cannonlake_rvp') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 627e7d25a6..b80cd82d50 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -33,6 +33,9 @@ chip soc/intel/cannonlake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index d417e9057e..9a0ab64672 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -33,6 +33,9 @@ chip soc/intel/cannonlake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHda" = "1" + register "PcieRpEnable[0]" = "1" register "PcieRpEnable[1]" = "1" register "PcieRpEnable[2]" = "1" -- cgit v1.2.3