From 530c6f9cc8dd2c0cd0c586d3d14f11cb8021242f Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 13 Oct 2017 15:15:48 -0700 Subject: intel/cannonlake_rvp: enable HS400 Set SCS emmc HS400 enable FSP parameter. TEST=Boot to OS, verify HS400 SDHCI print Change-Id: I3ef8a6740ef985a0c51115d9b0ea753b5db2c70d Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/22008 Reviewed-by: Lijian Zhao Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Pratikkumar V Prajapati --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 1 + src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 1 + 2 files changed, 2 insertions(+) (limited to 'src/mainboard/intel/cannonlake_rvp') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 00c3e0020e..54d2a69a0f 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -9,6 +9,7 @@ chip soc/intel/cannonlake register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 086d650737..bb75605b11 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -9,6 +9,7 @@ chip soc/intel/cannonlake register "FspSkipMpInit" = "1" register "SmbusEnable" = "1" register "ScsEmmcEnabled" = "1" + register "ScsEmmcHs400Enabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" -- cgit v1.2.3