From 14cb828f4fd818c4d9d1bcf80db9e5a9fc2df19f Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Thu, 12 Oct 2017 16:55:54 -0700 Subject: intel/cannonlake_rvp: Modify memory parameters to support LP4 board Replace the support for Cannonlake U DDR4 board to Cannonlake U LPDDR4 platform. TEST=Able to boot up on CNL U LPDDR RVP. Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/22001 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Martin Roth Reviewed-by: Aaron Durbin --- src/mainboard/intel/cannonlake_rvp/romstage.c | 16 ++++--------- src/mainboard/intel/cannonlake_rvp/spd/spd_util.c | 28 +++++------------------ 2 files changed, 10 insertions(+), 34 deletions(-) (limited to 'src/mainboard/intel/cannonlake_rvp') diff --git a/src/mainboard/intel/cannonlake_rvp/romstage.c b/src/mainboard/intel/cannonlake_rvp/romstage.c index 03c5807c00..e0699da500 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage.c @@ -36,18 +36,10 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) mainboard_fill_rcomp_res_data(&mem_cfg->RcompResistor); mainboard_fill_rcomp_strength_data(&mem_cfg->RcompTarget); - if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) { - mem_cfg->DqPinsInterleaved = 1; - mem_cfg->CaVrefConfig = 2; /* VREF_CA->CHA VREF_DQ_B->CHB */ - spd_index = 1; - } else { /* For CONFIG_BOARD_INTEL_CANNONLAKE_RVPY */ - mem_cfg->DqPinsInterleaved = 0; - mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ - mem_cfg->ECT = 1; /* Early Command Training Enabled */ - spd_index = 2; - } - - printk(BIOS_DEBUG,"SPD INDEX =0x%u\n", spd_index); + mem_cfg->DqPinsInterleaved = 0; + mem_cfg->CaVrefConfig = 0; /* VREF_CA->CHA/CHB */ + mem_cfg->ECT = 1; /* Early Command Training Enabled */ + spd_index = 2; struct region_device spd_rdev; diff --git a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c index 1e95280d74..4e2f31fc4b 100644 --- a/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c +++ b/src/mainboard/intel/cannonlake_rvp/spd/spd_util.c @@ -31,25 +31,17 @@ void mainboard_fill_dq_map_ch0(void *dq_map_ptr) void mainboard_fill_dq_map_ch1(void *dq_map_ptr) { - /* DQ byte map Ch1 */ - const u8 dq_map_u[12] = { - 0x33, 0xCC, 0x33, 0xCC, 0xFF, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - - const u8 dq_map_y[12] = { + const u8 dq_map[12] = { 0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; - if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) - memcpy(dq_map_ptr, dq_map_u, sizeof(dq_map_u)); - else - memcpy(dq_map_ptr, dq_map_y, sizeof(dq_map_y)); + memcpy(dq_map_ptr, dq_map, sizeof(dq_map)); } void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch0 */ - const u8 dqs_map_u[8] = { 0, 1, 3, 2, 4, 5, 6, 7 }; + const u8 dqs_map_u[8] = { 0, 3, 2, 1, 5, 6, 7, 4 }; const u8 dqs_map_y[8] = { 2, 0, 3, 1, 6, 5, 7, 4 }; @@ -62,7 +54,7 @@ void mainboard_fill_dqs_map_ch0(void *dqs_map_ptr) void mainboard_fill_dqs_map_ch1(void *dqs_map_ptr) { /* DQS CPU<>DRAM map Ch1 */ - const u8 dqs_map_u[8] = { 1, 0, 4, 5, 2, 3, 6, 7 }; + const u8 dqs_map_u[8] = { 3, 0, 1, 2, 5, 6, 4, 7 }; const u8 dqs_map_y[8] = { 3, 1, 2, 0, 4, 5, 6, 7 }; @@ -82,16 +74,8 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { /* Rcomp target */ - static const u16 RcompTarget_U[RCOMP_TARGET_PARAMS] = { - 100, 33, 32, 33, 28 }; - - static const u16 RcompTarget_Y[RCOMP_TARGET_PARAMS] = { + static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { 80, 40, 40, 40, 30 }; - if (IS_ENABLED(CONFIG_BOARD_INTEL_CANNONLAKE_RVPU)) - memcpy(rcomp_strength_ptr, RcompTarget_U, - sizeof(RcompTarget_U)); - else - memcpy(rcomp_strength_ptr, RcompTarget_Y, - sizeof(RcompTarget_Y)); + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } -- cgit v1.2.3