From 119ace0908b66b718c4b581423309648b10e4bf7 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 2 Oct 2019 16:02:06 +0200 Subject: soc/intel/cnl: Configure FSP option PcieRpSlotImplemented Allow configuring FSP option PcieRpSlotImplemented. Also, update all related devicetrees and configure PcieRpSlotImplemented to keep the current behaviour. Change-Id: I6c57ab0ae50a37cd9a90786134e9056851a86a3c Signed-off-by: Nico Huber Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/39986 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- .../intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 12 +++++++++--- .../intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 12 +++++++++--- 2 files changed, 18 insertions(+), 6 deletions(-) (limited to 'src/mainboard/intel/cannonlake_rvp') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index e5f867cbdc..f24e191256 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -124,12 +124,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index 53c677b64e..6f282f05a4 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -140,12 +140,18 @@ chip soc/intel/cannonlake device pci 19.1 off end # I2C #5 device pci 19.2 on end # UART #2 device pci 1a.0 on end # eMMC - device pci 1c.0 on end # PCI Express Port 1 x4 SLOT1 - device pci 1c.4 on end # PCI Express Port 5 x1 SLOT2/LAN + device pci 1c.0 on # PCI Express Port 1 x4 SLOT1 + register "PcieRpSlotImplemented[0]" = "1" + end + device pci 1c.4 on # PCI Express Port 5 x1 SLOT2/LAN + register "PcieRpSlotImplemented[4]" = "1" + end device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 on # PCI Express Port 9 + register "PcieRpSlotImplemented[8]" = "1" + end device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 -- cgit v1.2.3