From b269f873b0a0d43911adc907a53bbebadc742b78 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 31 Jul 2018 17:23:32 -0700 Subject: soc/intel/cannonlake: Update UPD from device switch Some of the FSP silicon UPD entry can be updated base on device switch in pci device tree, have both static config setting and device tree "on" and "off" will be redundant. BUG=N/A TEST=Build and boot up fine with Whiskey Lake RVP platform. Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/27766 Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb | 2 -- src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb | 2 -- 2 files changed, 4 deletions(-) (limited to 'src/mainboard/intel/cannonlake_rvp/variants') diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb index 6bd90a55ac..3357140fc1 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" diff --git a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb index bff470b02d..8491766e07 100644 --- a/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb +++ b/src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb @@ -7,9 +7,7 @@ chip soc/intel/cannonlake # FSP configuration register "SaGv" = "3" register "SmbusEnable" = "1" - register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" - register "ScsSdCardEnabled" = "1" register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)" register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC0)" -- cgit v1.2.3