From 6c0f3c7ee1d53872851dbab636787852e3572c98 Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 29 Aug 2017 17:12:51 -0700 Subject: soc/intel/cannonlake: Add dummy ACPI DSDT table A dummy DSDT table will be created for cannonlake. Change-Id: Ia435f2a03982313c6b0c63ac25668a3300d08793 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/21279 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/cannonlake_rvp/dsdt.asl | 37 +++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 src/mainboard/intel/cannonlake_rvp/dsdt.asl (limited to 'src/mainboard/intel/cannonlake_rvp/dsdt.asl') diff --git a/src/mainboard/intel/cannonlake_rvp/dsdt.asl b/src/mainboard/intel/cannonlake_rvp/dsdt.asl new file mode 100644 index 0000000000..410e1aca6c --- /dev/null +++ b/src/mainboard/intel/cannonlake_rvp/dsdt.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2017 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // global NVS and variables + #include + + Scope (\_SB) { + } + +#if IS_ENABLED(CONFIG_CHROMEOS) + // Chrome OS specific + #include +#endif +} -- cgit v1.2.3