From 454625c5cf4adecb5b80777503bc600c8b139004 Mon Sep 17 00:00:00 2001 From: Kayalvizhi Dhandapani Date: Tue, 7 Oct 2014 14:34:01 -0400 Subject: intel/fsp_baytrail: Fix SMM/SMI With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485 Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani Reviewed-on: http://review.coreboot.org/7026 Reviewed-by: Paul Menzel Reviewed-by: Marc Jones Tested-by: build bot (Jenkins) --- src/mainboard/intel/bayleybay_fsp/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/intel/bayleybay_fsp') diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb index befd3dce25..356c8df5f3 100644 --- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb +++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb @@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail register "SataMode" = "SATA_MODE_AHCI" register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT" + register "MrcInitTsegSize" = "TSEG_SIZE_8_MB" register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" -- cgit v1.2.3