From 6d5e10c05d99c475e63bbe95012066f9c585cfb3 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Wed, 14 Mar 2018 19:57:16 -0700 Subject: soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin array This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/apollolake_rvp/devicetree.cb | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mainboard/intel/apollolake_rvp') diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb index 746aaf31b2..f7e82a06ca 100644 --- a/src/mainboard/intel/apollolake_rvp/devicetree.cb +++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb @@ -1,11 +1,11 @@ chip soc/intel/apollolake - register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 - register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot - register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 - register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" - register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[0]" = "2" # PCIe slot 2 + register "pcie_rp_clkreq_pin[1]" = "3" # Wifi+BT M2 slot + register "pcie_rp_clkreq_pin[2]" = "0" # PCIe slot 1 + register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" device cpu_cluster 0 on device lapic 0 on end -- cgit v1.2.3