From f51b12735d822289942d8958707f400bc9634d00 Mon Sep 17 00:00:00 2001 From: Lance Zhao Date: Mon, 9 Nov 2015 17:06:34 -0800 Subject: soc/apollolake: Add skeleton ACPI entry Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao Reviewed-on: https://review.coreboot.org/13348 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 src/mainboard/intel/apollolake_rvp/dsdt.asl (limited to 'src/mainboard/intel/apollolake_rvp/dsdt.asl') diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000000..7b9fe29759 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} -- cgit v1.2.3