From cffc938934a9ee3b344ef594874e55f131bea77b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 29 Jan 2021 18:41:35 +0530 Subject: soc/intel/alderlake: Create separate Kconfig for CLKSRC and CLKREQ As per Hardware Architecture Specification (HAS) ADL-P has 7 CLKSRC and 10 CLKREQ (7 SRCCLK is internal and 3 SRCCLK from external CLK chip). ADL-M has 6 SRCCLK and CLKREQ (no external CLK chip). Change-Id: I7d223c165f819669722cbc80245fa8ec20372352 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/50130 Reviewed-by: EricR Lai Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mainboard/intel/adlrvp') diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index f2a8f3779a..0dd1456d42 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -84,9 +84,6 @@ chip soc/intel/alderlake register "PchPcieRpEnable[2]" = "1" register "PchPcieRpEnable[3]" = "1" - # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below - register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED" - register "SataSalpSupport" = "1" register "SataPortsEnable" = "{ -- cgit v1.2.3