From a1c247b55dfc182b365ac0630fc615277017631e Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Thu, 31 Dec 2020 22:50:14 -0800 Subject: soc/intel/adl and mb/intel/adlrvp: Use the newly added meminit block driver This change uses the newly added meminit block driver and updates ADL SoC and mainboard code accordingly. BUG=b:172978729 Change-Id: Ibcc4ee685cdd70eac99f12a5b5d79fdbaf2b3cf6 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/49043 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak Reviewed-by: Meera Ravindranath Reviewed-by: EricR Lai Reviewed-by: Subrata Banik --- src/mainboard/intel/adlrvp/memory.c | 156 +++++++++++++++++------ src/mainboard/intel/adlrvp/romstage_fsp_params.c | 24 ++-- 2 files changed, 127 insertions(+), 53 deletions(-) (limited to 'src/mainboard/intel/adlrvp') diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index 80ec14aa17..8d6aae96eb 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -6,84 +6,156 @@ #include static const struct mb_cfg ddr4_mem_config = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* Baseboard Rcomp target values */ - .rcomp_targets = {40, 30, 33, 33, 30}, - - .dq_pins_interleaved = false, + .type = MEM_TYPE_DDR4, .ect = true, /* Early Command Training */ .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .dq_pins_interleaved = false, + }, }; static const struct mb_cfg lpddr4_mem_config = { + .type = MEM_TYPE_LP4X, + /* DQ byte map */ - .dq_map = { - { 0, 2, 3, 1, 6, 7, 5, 4, 10, 8, 11, 9, 14, 12, 13, 15 }, - { 12, 8, 14, 10, 11, 13, 15, 9, 5, 0, 7, 3, 6, 2, 1, 4 }, - { 3, 0, 2, 1, 6, 5, 4, 7, 12, 13, 14, 15, 10, 9, 8, 11 }, - { 2, 6, 7, 1, 3, 4, 0, 5, 9, 13, 8, 15, 14, 11, 12, 10 }, - { 3, 0, 1, 2, 7, 4, 6, 5, 10, 8, 11, 9, 14, 13, 12, 15 }, - { 10, 12, 14, 8, 9, 13, 15, 11, 3, 7, 6, 2, 0, 4, 5, 1 }, - { 12, 15, 14, 13, 9, 10, 11, 8, 7, 4, 6, 5, 0, 1, 3, 2 }, - { 0, 2, 4, 3, 1, 6, 7, 5, 13, 9, 10, 11, 8, 12, 14, 15 }, + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 0, 2, 3, 1, 6, 7, 5, 4, }, + .dq1 = { 10, 8, 11, 9, 14, 12, 13, 15, }, + }, + .ddr1 = { + .dq0 = { 12, 8, 14, 10, 11, 13, 15, 9, }, + .dq1 = { 5, 0, 7, 3, 6, 2, 1, 4, }, + }, + .ddr2 = { + .dq0 = { 3, 0, 2, 1, 6, 5, 4, 7, }, + .dq1 = { 12, 13, 14, 15, 10, 9, 8, 11, }, + }, + .ddr3 = { + .dq0 = { 2, 6, 7, 1, 3, 4, 0, 5, }, + .dq1 = { 9, 13, 8, 15, 14, 11, 12, 10, }, + }, + .ddr4 = { + .dq0 = { 3, 0, 1, 2, 7, 4, 6, 5, }, + .dq1 = { 10, 8, 11, 9, 14, 13, 12, 15, }, + }, + .ddr5 = { + .dq0 = { 10, 12, 14, 8, 9, 13, 15, 11, }, + .dq1 = { 3, 7, 6, 2, 0, 4, 5, 1, }, + }, + .ddr6 = { + .dq0 = { 12, 15, 14, 13, 9, 10, 11, 8, }, + .dq1 = { 7, 4, 6, 5, 0, 1, 3, 2, }, + }, + .ddr7 = { + .dq0 = { 0, 2, 4, 3, 1, 6, 7, 5, }, + .dq1 = { 13, 9, 10, 11, 8, 12, 14, 15, }, + }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, }, - .dq_pins_interleaved = false, - .ect = true, /* Early Command Training */ .UserBd = BOARD_TYPE_MOBILE, }; static const struct mb_cfg lp5_mem_config = { + .type = MEM_TYPE_LP5X, /* DQ byte map */ - .dq_map = { - { 3, 2, 1, 0, 5, 4, 6, 7, 15, 14, 12, 13, 8, 9, 10, 11 }, - { 0, 2, 3, 1, 5, 7, 4, 6, 14, 13, 15, 12, 8, 9, 11, 10 }, - { 1, 2, 0, 3, 4, 6, 5, 7, 15, 13, 12, 14, 9, 10, 8, 11 }, - { 2, 1, 3, 0, 7, 4, 5, 6, 13, 12, 15, 14, 9, 11, 8, 10 }, - { 1, 2, 3, 0, 6, 4, 5, 7, 15, 13, 14, 12, 10, 9, 8, 11 }, - { 1, 0, 3, 2, 6, 7, 4, 5, 14, 12, 15, 13, 8, 9, 10, 11 }, - { 0, 2, 1, 3, 4, 7, 5, 6, 12, 13, 15, 14, 9, 11, 10, 8 }, - { 3, 2, 1, 0, 5, 4, 6, 7, 13, 15, 11, 12, 10, 9, 14, 8 }, + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 15, 14, 12, 13, 8, 9, 10, 11, }, + }, + .ddr1 = { + .dq0 = { 0, 2, 3, 1, 5, 7, 4, 6, }, + .dq1 = { 14, 13, 15, 12, 8, 9, 11, 10, }, + }, + .ddr2 = { + .dq0 = { 1, 2, 0, 3, 4, 6, 5, 7, }, + .dq1 = { 15, 13, 12, 14, 9, 10, 8, 11, }, + }, + .ddr3 = { + .dq0 = { 2, 1, 3, 0, 7, 4, 5, 6, }, + .dq1 = { 13, 12, 15, 14, 9, 11, 8, 10, }, + }, + .ddr4 = { + .dq0 = { 1, 2, 3, 0, 6, 4, 5, 7, }, + .dq1 = { 15, 13, 14, 12, 10, 9, 8, 11, }, + }, + .ddr5 = { + .dq0 = { 1, 0, 3, 2, 6, 7, 4, 5, }, + .dq1 = { 14, 12, 15, 13, 8, 9, 10, 11, }, + }, + .ddr6 = { + .dq0 = { 0, 2, 1, 3, 4, 7, 5, 6, }, + .dq1 = { 12, 13, 15, 14, 9, 11, 10, 8, }, + }, + .ddr7 = { + .dq0 = { 3, 2, 1, 0, 5, 4, 6, 7, }, + .dq1 = { 13, 15, 11, 12, 10, 9, 14, 8, }, + }, }, /* DQS CPU<>DRAM map */ - .dqs_map = { - { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 } + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } }, - .dq_pins_interleaved = false, - .ect = false, /* Early Command Training */ - .lp5_ccc_config = 0xff, - .UserBd = BOARD_TYPE_MOBILE, + + .lp5x_config = { + .ccc_config = 0xff, + }, }; static const struct mb_cfg ddr5_mem_config = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* Baseboard Rcomp target values */ - .rcomp_targets = {50, 30, 30, 30, 27}, - - .dq_pins_interleaved = false, + .type = MEM_TYPE_DDR5, .ect = true, /* Early Command Training */ .UserBd = BOARD_TYPE_MOBILE, + + .ddr_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {50, 30, 30, 30, 27}, + + .dq_pins_interleaved = false, + } }; const struct mb_cfg *variant_memory_params(void) diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index 2f03cb4e84..50ba1b3c05 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -31,19 +31,21 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) int board_id = get_board_id(); const bool half_populated = false; - const struct spd_info lp4_lp5_spd_info = { - .read_type = READ_SPD_CBFS, - .spd_spec.spd_index = get_spd_index(), + const struct mem_spd lp4_lp5_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = get_spd_index(), }; - const struct spd_info ddr4_ddr5_spd_info = { - .read_type = READ_SMBUS, - .spd_spec = { - .spd_smbus_address = { - [0] = 0xa0, - [1] = 0xa2, - [8] = 0xa4, - [9] = 0xa6, + const struct mem_spd ddr4_ddr5_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0xa0, + .addr_dimm[1] = 0xa2, + }, + [1] = { + .addr_dimm[0] = 0xa4, + .addr_dimm[1] = 0xa6, }, }, }; -- cgit v1.2.3