From 6147314344ae257081ec91dd709b18da283878fc Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 14 Oct 2020 22:06:48 +0530 Subject: mb/intel/adlrvp: Enable PCIE RP11 for optane A regular M.2 NVMe SSD shows up on RP9 and runs at x4 width. Optane memory module shows up as 2 NVMe devices in x2 config: - NVMe storage device uses RP9 - NVMe Optane memory uses RP11 Note: These two devices are sharing CLK PINs because of same M.2 slot. TEST=Build and boot ADL RVP board using Intel Optane card. Change-Id: Ia21d7d2fd07c4fb32291af7bb5a2e41e40316278 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46419 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/adlrvp') diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb index afa4c19098..fadf602536 100644 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb @@ -59,6 +59,9 @@ chip soc/intel/alderlake register "PcieClkSrcUsage[1]" = "0x8" register "PcieRpClkReqDetect[8]" = "1" + # Enable PCH PCIE RP 11 for optane + register "PcieRpEnable[10]" = "1" + # Enable CPU PCIE RP 1 using PEG CLK 0 register "PcieClkSrcUsage[0]" = "0x40" @@ -241,7 +244,7 @@ chip soc/intel/alderlake device pci 1c.7 off end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 - device pci 1d.2 off end # RP11 + device pci 1d.2 on end # RP11 device pci 1d.3 off end # RP12 device pci 1e.0 on end # UART0 device pci 1e.1 off end # UART1 -- cgit v1.2.3