From 0a61ecef35f0b72c747961e5c0eb14f800b10d8a Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 7 Nov 2020 13:01:49 +0530 Subject: mb/intel/adlrvp: Refactor ADLRVP code to get rid of 'variants/baseboard' List of changes: 1. Use devicetree.cb from default location 2. Create variant directory for ADL RVP with external EC as 'adlrvp_p_ext_ec' 3. Add initial overridetree.cb for 'adlrvp_p' and 'adlrvp_p_ext_ec' to override 'devicetree.cb' as applicable. 4. Move all common files between 'adlrvp_p' and 'adlrvp_p_ext_ec' to mainboard directory TEST=Build and boot both ADLRVP with onboard and external EC. Change-Id: I3591e214ed32dc9baaa49b92dff59579f29c7bd6 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47335 Reviewed-by: V Sowmya Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/Kconfig | 7 +- src/mainboard/intel/adlrvp/Makefile.inc | 6 +- src/mainboard/intel/adlrvp/devicetree.cb | 274 ++++++++++++++++++ src/mainboard/intel/adlrvp/early_gpio.c | 19 ++ src/mainboard/intel/adlrvp/gpio.c | 305 +++++++++++++++++++++ src/mainboard/intel/adlrvp/include/baseboard/ec.h | 73 +++++ .../intel/adlrvp/include/baseboard/gpio.h | 18 ++ .../intel/adlrvp/include/baseboard/variants.h | 31 +++ src/mainboard/intel/adlrvp/memory.c | 83 ++++++ .../intel/adlrvp/variants/adlrvp_p/Makefile.inc | 7 - .../intel/adlrvp/variants/adlrvp_p/devicetree.cb | 274 ------------------ .../intel/adlrvp/variants/adlrvp_p/early_gpio.c | 19 -- .../intel/adlrvp/variants/adlrvp_p/gpio.c | 305 --------------------- .../intel/adlrvp/variants/adlrvp_p/memory.c | 83 ------ .../intel/adlrvp/variants/adlrvp_p/overridetree.cb | 4 + .../variants/adlrvp_p_ext_ec/overridetree.cb | 4 + .../variants/baseboard/include/baseboard/ec.h | 73 ----- .../variants/baseboard/include/baseboard/gpio.h | 18 -- .../baseboard/include/baseboard/variants.h | 31 --- 19 files changed, 819 insertions(+), 815 deletions(-) create mode 100644 src/mainboard/intel/adlrvp/devicetree.cb create mode 100644 src/mainboard/intel/adlrvp/early_gpio.c create mode 100644 src/mainboard/intel/adlrvp/gpio.c create mode 100644 src/mainboard/intel/adlrvp/include/baseboard/ec.h create mode 100644 src/mainboard/intel/adlrvp/include/baseboard/gpio.h create mode 100644 src/mainboard/intel/adlrvp/include/baseboard/variants.h create mode 100644 src/mainboard/intel/adlrvp/memory.c delete mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc delete mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb delete mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c delete mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c delete mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c create mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb create mode 100644 src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb delete mode 100644 src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h delete mode 100644 src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h delete mode 100644 src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h (limited to 'src/mainboard/intel/adlrvp') diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 2a3dbb021c..a41c18659d 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -32,7 +32,8 @@ config MAINBOARD_DIR config VARIANT_DIR string - default "adlrvp_p" + default "adlrvp_p" if BOARD_INTEL_ADLRVP_P + default "adlrvp_p_ext_ec" if BOARD_INTEL_ADLRVP_P_EXT_EC config GBB_HWID string @@ -47,9 +48,9 @@ config MAINBOARD_FAMILY string default "Intel_adlrvp" -config DEVICETREE +config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config DIMM_SPD_SIZE int diff --git a/src/mainboard/intel/adlrvp/Makefile.inc b/src/mainboard/intel/adlrvp/Makefile.inc index 2ca32f3760..de924067d1 100644 --- a/src/mainboard/intel/adlrvp/Makefile.inc +++ b/src/mainboard/intel/adlrvp/Makefile.inc @@ -4,12 +4,14 @@ subdirs-y += spd bootblock-y += bootblock.c bootblock-$(CONFIG_CHROMEOS) += chromeos.c +bootblock-y += early_gpio.c verstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += romstage_fsp_params.c romstage-y += board_id.c +romstage-y += memory.c smm-y += smihandler.c @@ -17,8 +19,8 @@ ramstage-$(CONFIG_CHROMEOS) += chromeos.c ramstage-y += ec.c ramstage-y += mainboard.c ramstage-y += board_id.c +ramstage-y += gpio.c -subdirs-y += variants/baseboard -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb new file mode 100644 index 0000000000..ce55fa3914 --- /dev/null +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -0,0 +1,274 @@ +chip soc/intel/alderlake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + register "pmc_gpe0_dw0" = "GPP_B" + register "pmc_gpe0_dw1" = "GPP_D" + register "pmc_gpe0_dw2" = "GPP_E" + + # FSP configuration + + register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 + register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 + register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN + register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector + register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 + register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 + register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN + + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x000c0201" + # EC memory map range is 0x900-0x9ff + register "gen3_dec" = "0x00fc0901" + register "gen4_dec" = "0x000c0081" + + register "PrmrrSize" = "0" + + # Enable PCH PCIE RP 5 using CLK 2 + register "PcieRpEnable[4]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcUsage[2]" = "0x4" + register "PcieRpClkReqDetect[4]" = "1" + + # Enable PCH PCIE RP 6 using CLK 5 + register "PcieRpEnable[5]" = "1" + register "PcieClkSrcClkReq[5]" = "5" + register "PcieClkSrcUsage[5]" = "0x5" + register "PcieRpClkReqDetect[5]" = "1" + + # Enable PCH PCIE RP 9 using CLK 1 + register "PcieRpEnable[8]" = "1" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcUsage[1]" = "0x8" + register "PcieRpClkReqDetect[8]" = "1" + + # Enable PCH PCIE RP 11 for optane + register "PcieRpEnable[10]" = "1" + # Hybrid storage mode + register "HybridStorageMode" = "1" + + # Enable CPU PCIE RP 1 using PEG CLK 0 + register "PcieClkSrcUsage[0]" = "0x40" + + # Enable PCU PCIE PEG Slot 1 and 2 + register "PcieClkSrcUsage[3]" = "0x41" + register "PcieClkSrcUsage[4]" = "0x42" + + # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below + register "PcieClkSrcUsage[6]" = "0xff" + + register "SataSalpSupport" = "1" + + register "SataPortsEnable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + register "SataPortsDevSlp" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + }" + + # Enable EDP in PortA + register "DdiPortAConfig" = "1" + register "DdiPortBConfig" = "1" + + # TCSS USB3 + register "TcssAuxOri" = "0" + + register "s0ix_enable" = "1" + + register "SerialIoI2cMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoPci, + [PchSerialIoIndexI2C1] = PchSerialIoPci, + [PchSerialIoIndexI2C2] = PchSerialIoPci, + [PchSerialIoIndexI2C3] = PchSerialIoPci, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoPci, + }" + + register "SerialIoGSpiMode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, + }" + + register "SerialIoGSpiCsMode" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoGSpiCsState" = "{ + [PchSerialIoIndexGSPI0] = 0, + [PchSerialIoIndexGSPI1] = 0, + [PchSerialIoIndexGSPI2] = 0, + [PchSerialIoIndexGSPI3] = 0, + }" + + register "SerialIoUartMode" = "{ + [PchSerialIoIndexUART0] = PchSerialIoSkipInit, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # HD Audio + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "0" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "1" + register "PchHdaAudioLinkSndwEnable[0]" = "1" + register "PchHdaAudioLinkSndwEnable[1]" = "1" + # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T + register "PchHdaIDispLinkTmode" = "2" + # iDisp-Link Freq 4: 96MHz, 3: 48MHz. + register "PchHdaIDispLinkFrequency" = "4" + # Not disconnected/enumerable + register "PchHdaIDispCodecDisconnect" = "0" + + # Intel Common SoC Config + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Graphics + device pci 04.0 on end # DPTF + device pci 05.0 on end # IPU + device pci 06.0 on end # PEG60 + device pci 07.0 on end # TBT_PCIe0 + device pci 07.1 on end # TBT_PCIe1 + device pci 07.2 on end # TBT_PCIe2 + device pci 07.3 on end # TBT_PCIe3 + device pci 08.0 off end # GNA + device pci 09.0 off end # NPK + device pci 0a.0 off end # Crash-log SRAM + device pci 0d.0 on end # USB xHCI + device pci 0d.1 on end # USB xDCI (OTG) + device pci 0d.2 on end # TBT DMA0 + device pci 0d.3 on end # TBT DMA1 + device pci 0e.0 off end # VMD + device pci 10.0 off end + device pci 10.1 off end + device pci 10.2 on end # CNVi: BT + device pci 10.6 off end # THC0 + device pci 10.7 off end # THC1 + device pci 11.0 off end + device pci 11.1 off end + device pci 11.2 off end + device pci 11.3 off end + device pci 11.4 off end + device pci 11.5 off end + device pci 12.0 off end # SensorHUB + device pci 12.5 off end + device pci 12.6 off end # GSPI2 + device pci 13.0 off end # GSPI3 + device pci 13.1 off end + device pci 14.0 on + chip drivers/usb/acpi + register "desc" = ""Root Hub"" + register "type" = "UPC_TYPE_HUB" + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device usb 2.9 on end + end + end + end + end # USB3.1 xHCI + device pci 14.1 off end # USB3.1 xDCI + device pci 14.2 off end # Shared RAM + device pci 14.3 on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end # CNVi: WiFi + device pci 15.0 on end # I2C0 + device pci 15.1 on end # I2C1 + device pci 15.2 on end # I2C2 + device pci 15.3 on end # I2C3 + device pci 16.0 on end # HECI1 + device pci 16.1 off end # HECI2 + device pci 16.2 off end # CSME + device pci 16.3 off end # CSME + device pci 16.4 off end # HECI3 + device pci 16.5 off end # HECI4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C4 + device pci 19.1 on end # I2C5 + device pci 19.2 off end # UART2 + device pci 1c.0 on end # RP1 + device pci 1c.1 off end # RP2 + device pci 1c.2 off end # RP3 + device pci 1c.3 off end # RP4 + device pci 1c.4 on end # RP5 + device pci 1c.5 on end # RP6 + device pci 1c.6 off end # RP7 + device pci 1c.7 off end # RP8 + device pci 1d.0 on end # RP9 + device pci 1d.1 off end # RP10 + device pci 1d.2 on end # RP11 + device pci 1d.3 off end # RP12 + device pci 1e.0 on end # UART0 + device pci 1e.1 off end # UART1 + device pci 1e.2 on end # GSPI0 + device pci 1e.3 off end # GSPI1 + device pci 1f.0 on end # eSPI + device pci 1f.1 on end # P2SB + device pci 1f.2 hidden end # PMC + device pci 1f.3 on + chip drivers/intel/soundwire + device generic 0 on + chip drivers/soundwire/alc711 + # SoundWire Link 0 ID 1 + register "desc" = ""Headset Codec"" + device generic 0.1 on end + end + end + end + end # Intel Audio SNDW + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # SPI + device pci 1f.6 off end # GbE + device pci 1f.7 off end # TH + end +end diff --git a/src/mainboard/intel/adlrvp/early_gpio.c b/src/mainboard/intel/adlrvp/early_gpio.c new file mode 100644 index 0000000000..d45bf8e067 --- /dev/null +++ b/src/mainboard/intel/adlrvp/early_gpio.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 0, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), +}; + +void variant_configure_early_gpio_pads(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c new file mode 100644 index 0000000000..f91b94faf4 --- /dev/null +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -0,0 +1,305 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage*/ +static const struct pad_config gpio_table[] = { + /* SSD1_PWREN CPU SSD1 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + /* SSD1_RESET CPU SSD1 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + /* BT_RF_KILL_N */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + /* WLAN RST# */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + /* WIFI_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), + /* x4 PCIE slot1 PWREN */ + PAD_CFG_GPO(GPP_H17, 0, PLTRST), + /* x4 PCIE slot 1 RESET */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + /* Retimer Force Power */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + /* PEG Slot RST# */ + PAD_CFG_GPO(GPP_B2, 1, PLTRST), + /* M.2 SSD_2 Reset */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + /* CAM1-IRQ */ + PAD_CFG_GPO(GPP_B23, 1, PLTRST), + /* CAM_STROBE */ + PAD_CFG_GPO(GPP_B18, 0, PLTRST), + /* Audio Codec INT N */ + PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), + /* TCH PAD Power EN */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* THC1 SPI2 RST# */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), + /* THC1_SPI2_INTB */ + PAD_CFG_GPI(GPP_E17, NONE, PLTRST), + /* EC_SMI_N */ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE), + /* EC_SLP_S0_CS_N */ + PAD_CFG_GPO(GPP_F9, 1, PLTRST), + /* WIFI RF KILL */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + /* DISP_AUX_N_BIAS_GPIO */ + PAD_CFG_GPO(GPP_E23, 1, PLTRST), + /* WWAN WAKE N*/ + PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), + /* WWAN_DISABLE_N */ + PAD_CFG_GPO(GPP_D15, 1, PLTRST), + /* WWAN_RST# */ + PAD_CFG_GPO(GPP_E10, 1, PLTRST), + /* WWAN_PWR_EN */ + PAD_CFG_GPO(GPP_E13, 1, DEEP), + /* WWAN_PERST# */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + /* PEG_SLOT_WAKE_N */ + PAD_CFG_GPI(GPP_A20, NONE, PLTRST), + /* UART_BT_WAKE_N */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), + /* CAM CONN1 CLKEN */ + PAD_CFG_GPO(GPP_H15, 1, PLTRST), + /* CPU SSD2 PWREN */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + /* CPU SSD2 RST# */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + /* Sata direct Power */ + PAD_CFG_GPO(GPP_B4, 1, PLTRST), + /* M.2_PCH_SSD_PWREN */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + + /* M.2_SSD_PDET_R */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* THC0 SPI1 CLK */ + PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), + /* THC0 SPI1 IO 1 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), + /* THC0 SPI1 IO 2 */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), + /* THC0 SPI IO 3 */ + PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), + /* THC1 SPI1 RSTB */ + PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), + /* UART_RX(1) */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), + /* UART_RX(2) */ + PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), + /* UART_RX(4) */ + PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), + /* UART_RX(5) */ + PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), + /* UART_RX(6) */ + PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), + + /* UART_TX(1) */ + PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), + /* UART_TX(2) */ + PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), + /* UART_TX(4) */ + PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), + /* UART_TX(5) */ + PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), + /* UART_TX(6) */ + PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), + + /* UART_RTS(1) */ + PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), + /* UART_RTS(2) */ + PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), + /* UART_RTS(4) */ + PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), + /* UART_RTS(5) */ + PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), + /* UART_RTS(6) */ + PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), + + /* UART_CTS(1) */ + PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), + /* UART_CTS(2) */ + PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), + /* UART_CTS(4) */ + PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), + /* UART_CTS(5) */ + PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), + /* UART_CTS(6) */ + PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), + + /* SPI_MOSI(1) */ + PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), + /* SPI_MOSI(2) */ + PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), + + /* SPI_MIS0(0) */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* SPI_MIS0(1) */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* SPI_MIS0(2) */ + PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), + + /* SPI_CLK(0) */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* SPI_CLK(1) */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* SPI_CLK(2) */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), + + /* SPI_CS(0, 0) */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* SPI_CS(0, 1) */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* SPI_CS(1, 0) */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* SPI_CS(2, 0) */ + PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), + + /* I2C_SCL(0) */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* I2C_SCL(1) */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* I2C_SCL(2) */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* I2C_SCL(3) */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* I2C_SCL(5) */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* I2C_SCL(6) */ + PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), + /* I2C_SCL(7) */ + PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), + + /* I2C_SDA(0) */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* I2C_SDA(1) */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* I2C_SDA(2) */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* I2C_SDA(3) */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* I2C_SDA(5) */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* I2C_SDA(6) */ + PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), + /* I2C_SDA(7) */ + PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), + + /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* I2S0_TXD */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), + /* I2S0_RXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + + /* I2S1_SCLK */ + PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), + /* I2S1_SFRM */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), + /* I2S1_TXD */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), + /* I2S1_RXD */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), + + /* I2S2_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* I2S2_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* I2S2_TXD */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* I2S2_RXD */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* I2S_MCLK1_OUT */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), + /* I2S_MCLK2_INOUT */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + + /* SNDW1_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* SNDW1_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* SNDW2_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* SNDW2_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* SNDW3_CLK */ + PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), + /* SNDW3_DATA */ + PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), + /* SNDW4_CLK */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* SNDW4_DATA */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* SMB_CLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* SMB_DATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* SATADevSlpPin to GPIO pin mapping */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* SATA DIRECT DEVSLP*/ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + + /* SATA LED pin */ + PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), + + /* USB2 OC0 pins */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + /* USB2 OC1 pins */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), + /* USB2 OC2 pins */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), + /* USB2 OC3 pins */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPIO pin for PCIE SRCCLKREQB */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), + + /* HPD_1 (A19) and HPD_2 (A20) pins */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + + /* IMGCLKOUT */ + PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), +}; + +void variant_configure_gpio_pads(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), +}; + +const struct cros_gpio *variant_cros_gpios(size_t *num) +{ + *num = ARRAY_SIZE(cros_gpios); + return cros_gpios; +} diff --git a/src/mainboard/intel/adlrvp/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/include/baseboard/ec.h new file mode 100644 index 0000000000..4303faf0d2 --- /dev/null +++ b/src/mainboard/intel/adlrvp/include/baseboard/ec.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_EC_H__ +#define __BASEBOARD_EC_H__ + +#include +#include +#include + +#define MAINBOARD_EC_SCI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) + +#define MAINBOARD_EC_SMI_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) + +/* EC can wake from S5 with lid or power button */ +#define MAINBOARD_EC_S5_WAKE_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) + +/* + * EC can wake from S3 with lid or power button or key press or + * mode change event. + */ +#define MAINBOARD_EC_S3_WAKE_EVENTS \ + (MAINBOARD_EC_S5_WAKE_EVENTS |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) + +#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) + +/* Log EC wake events plus EC shutdown events */ +#define MAINBOARD_EC_LOG_EVENTS \ + (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ + EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) + +/* + * ACPI related definitions for ASL code. + */ + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* Enable LID switch and provide wake pin for EC */ +#define EC_ENABLE_LID_SWITCH +#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE + +#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ +#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ +#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ + +#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h new file mode 100644 index 0000000000..b61276c0c1 --- /dev/null +++ b/src/mainboard/intel/adlrvp/include/baseboard/gpio.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_GPIO_H__ +#define __BASEBOARD_GPIO_H__ + +#include +#include + +/* eSPI virtual wire reporting */ +#define EC_SCI_GPI GPE0_ESPI + +/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ +#define GPE_EC_WAKE GPE0_LAN_WAK + +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + +#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h new file mode 100644 index 0000000000..537e62451a --- /dev/null +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __BASEBOARD_VARIANTS_H__ +#define __BASEBOARD_VARIANTS_H__ + +#include +#include +#include +#include + +enum adl_boardid { + /* ADL-P LPDDR4 RVPs */ + ADL_P_LP4_1 = 0x10, + ADL_P_LP4_2 = 0x11, + /* ADL-P DDR5 RVPs */ + ADL_P_DDR5 = 0x12, + /* ADL-P DDR4 RVPs */ + ADL_P_DDR4_1 = 0x14, + ADL_P_DDR4_2 = 0x3F, +}; + +/* The next set of functions return the gpio table and fill in the number of + * entries for each table. */ +const struct cros_gpio *variant_cros_gpios(size_t *num); +/* Functions to configure GPIO as per variant schematics */ +void variant_configure_gpio_pads(void); +void variant_configure_early_gpio_pads(void); + +size_t variant_memory_sku(void); +const struct mb_cfg *variant_memory_params(void); +#endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c new file mode 100644 index 0000000000..d51caf783a --- /dev/null +++ b/src/mainboard/intel/adlrvp/memory.c @@ -0,0 +1,83 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "board_id.h" +#include +#include + +static const struct mb_cfg ddr4_mem_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {40, 30, 33, 33, 30}, + + .dq_pins_interleaved = true, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg lpddr4_mem_config = { + /* DQ byte map */ + .dq_map = { + { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ + 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ + { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ + 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ + { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ + 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ + { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ + 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ + { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ + 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ + { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ + 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ + { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ + 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ + { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ + 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + /* Ch 0 1 2 3 */ + { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, + { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } + }, + + .dq_pins_interleaved = false, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +static const struct mb_cfg ddr5_mem_config = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .rcomp_resistor = {100, 100, 100}, + + /* Baseboard Rcomp target values */ + .rcomp_targets = {50, 30, 30, 30, 27}, + + .dq_pins_interleaved = true, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + int board_id = get_board_id(); + + if (board_id == ADL_P_LP4_1 || board_id == ADL_P_LP4_2) + return &lpddr4_mem_config; + else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2) + return &ddr4_mem_config; + else if (board_id == ADL_P_DDR5) + return &ddr5_mem_config; + + die("unsupported board id : 0x%x\n", board_id); +} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc b/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc deleted file mode 100644 index 513963ebd5..0000000000 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/Makefile.inc +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -bootblock-y += early_gpio.c - -romstage-y += memory.c - -ramstage-y += gpio.c diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb deleted file mode 100644 index ce55fa3914..0000000000 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/devicetree.cb +++ /dev/null @@ -1,274 +0,0 @@ -chip soc/intel/alderlake - - device cpu_cluster 0 on - device lapic 0 on end - end - - # GPE configuration - # Note that GPE events called out in ASL code rely on this - # route. i.e. If this route changes then the affected GPE - # offset bits also need to be changed. - register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_D" - register "pmc_gpe0_dw2" = "GPP_E" - - # FSP configuration - - register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 - register "usb2_ports[1]" = "USB2_PORT_MID(OC0)" # Type-C Port2 - register "usb2_ports[2]" = "USB2_PORT_MID(OC3)" # Type-C Port3 - register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN - register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port4 - register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # FPS connector - register "usb2_ports[6]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port1 - register "usb2_ports[7]" = "USB2_PORT_MID(OC0)" # USB3/2 Type A port2 - register "usb2_ports[8]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port3 - register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WLAN - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC3)" # USB3/2 Type A port1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port2 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port3 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN - - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" - register "gen2_dec" = "0x000c0201" - # EC memory map range is 0x900-0x9ff - register "gen3_dec" = "0x00fc0901" - register "gen4_dec" = "0x000c0081" - - register "PrmrrSize" = "0" - - # Enable PCH PCIE RP 5 using CLK 2 - register "PcieRpEnable[4]" = "1" - register "PcieClkSrcClkReq[2]" = "2" - register "PcieClkSrcUsage[2]" = "0x4" - register "PcieRpClkReqDetect[4]" = "1" - - # Enable PCH PCIE RP 6 using CLK 5 - register "PcieRpEnable[5]" = "1" - register "PcieClkSrcClkReq[5]" = "5" - register "PcieClkSrcUsage[5]" = "0x5" - register "PcieRpClkReqDetect[5]" = "1" - - # Enable PCH PCIE RP 9 using CLK 1 - register "PcieRpEnable[8]" = "1" - register "PcieClkSrcClkReq[1]" = "1" - register "PcieClkSrcUsage[1]" = "0x8" - register "PcieRpClkReqDetect[8]" = "1" - - # Enable PCH PCIE RP 11 for optane - register "PcieRpEnable[10]" = "1" - # Hybrid storage mode - register "HybridStorageMode" = "1" - - # Enable CPU PCIE RP 1 using PEG CLK 0 - register "PcieClkSrcUsage[0]" = "0x40" - - # Enable PCU PCIE PEG Slot 1 and 2 - register "PcieClkSrcUsage[3]" = "0x41" - register "PcieClkSrcUsage[4]" = "0x42" - - # Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below - register "PcieClkSrcUsage[6]" = "0xff" - - register "SataSalpSupport" = "1" - - register "SataPortsEnable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" - - register "SataPortsDevSlp" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - }" - - # Enable EDP in PortA - register "DdiPortAConfig" = "1" - register "DdiPortBConfig" = "1" - - # TCSS USB3 - register "TcssAuxOri" = "0" - - register "s0ix_enable" = "1" - - register "SerialIoI2cMode" = "{ - [PchSerialIoIndexI2C0] = PchSerialIoPci, - [PchSerialIoIndexI2C1] = PchSerialIoPci, - [PchSerialIoIndexI2C2] = PchSerialIoPci, - [PchSerialIoIndexI2C3] = PchSerialIoPci, - [PchSerialIoIndexI2C4] = PchSerialIoDisabled, - [PchSerialIoIndexI2C5] = PchSerialIoPci, - }" - - register "SerialIoGSpiMode" = "{ - [PchSerialIoIndexGSPI0] = PchSerialIoPci, - [PchSerialIoIndexGSPI1] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI2] = PchSerialIoDisabled, - [PchSerialIoIndexGSPI3] = PchSerialIoDisabled, - }" - - register "SerialIoGSpiCsMode" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - [PchSerialIoIndexGSPI3] = 0, - }" - - register "SerialIoGSpiCsState" = "{ - [PchSerialIoIndexGSPI0] = 0, - [PchSerialIoIndexGSPI1] = 0, - [PchSerialIoIndexGSPI2] = 0, - [PchSerialIoIndexGSPI3] = 0, - }" - - register "SerialIoUartMode" = "{ - [PchSerialIoIndexUART0] = PchSerialIoSkipInit, - [PchSerialIoIndexUART1] = PchSerialIoDisabled, - [PchSerialIoIndexUART2] = PchSerialIoDisabled, - }" - - # HD Audio - register "PchHdaDspEnable" = "1" - register "PchHdaAudioLinkHdaEnable" = "0" - register "PchHdaAudioLinkDmicEnable[0]" = "1" - register "PchHdaAudioLinkDmicEnable[1]" = "1" - register "PchHdaAudioLinkSndwEnable[0]" = "1" - register "PchHdaAudioLinkSndwEnable[1]" = "1" - # iDisp-Link T-Mode 0: 2T, 2: 4T, 3: 8T, 4: 16T - register "PchHdaIDispLinkTmode" = "2" - # iDisp-Link Freq 4: 96MHz, 3: 48MHz. - register "PchHdaIDispLinkFrequency" = "4" - # Not disconnected/enumerable - register "PchHdaIDispCodecDisconnect" = "0" - - # Intel Common SoC Config - register "common_soc_config" = "{ - .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, - .i2c[0] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[1] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[2] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[3] = { - .speed = I2C_SPEED_FAST, - }, - .i2c[5] = { - .speed = I2C_SPEED_FAST, - }, - }" - - device domain 0 on - device pci 00.0 on end # Host Bridge - device pci 02.0 on end # Graphics - device pci 04.0 on end # DPTF - device pci 05.0 on end # IPU - device pci 06.0 on end # PEG60 - device pci 07.0 on end # TBT_PCIe0 - device pci 07.1 on end # TBT_PCIe1 - device pci 07.2 on end # TBT_PCIe2 - device pci 07.3 on end # TBT_PCIe3 - device pci 08.0 off end # GNA - device pci 09.0 off end # NPK - device pci 0a.0 off end # Crash-log SRAM - device pci 0d.0 on end # USB xHCI - device pci 0d.1 on end # USB xDCI (OTG) - device pci 0d.2 on end # TBT DMA0 - device pci 0d.3 on end # TBT DMA1 - device pci 0e.0 off end # VMD - device pci 10.0 off end - device pci 10.1 off end - device pci 10.2 on end # CNVi: BT - device pci 10.6 off end # THC0 - device pci 10.7 off end # THC1 - device pci 11.0 off end - device pci 11.1 off end - device pci 11.2 off end - device pci 11.3 off end - device pci 11.4 off end - device pci 11.5 off end - device pci 12.0 off end # SensorHUB - device pci 12.5 off end - device pci 12.6 off end # GSPI2 - device pci 13.0 off end # GSPI3 - device pci 13.1 off end - device pci 14.0 on - chip drivers/usb/acpi - register "desc" = ""Root Hub"" - register "type" = "UPC_TYPE_HUB" - device usb 0.0 on - chip drivers/usb/acpi - register "desc" = ""Bluetooth"" - register "type" = "UPC_TYPE_INTERNAL" - device usb 2.9 on end - end - end - end - end # USB3.1 xHCI - device pci 14.1 off end # USB3.1 xDCI - device pci 14.2 off end # Shared RAM - device pci 14.3 on - chip drivers/wifi/generic - register "wake" = "GPE0_PME_B0" - device generic 0 on end - end - end # CNVi: WiFi - device pci 15.0 on end # I2C0 - device pci 15.1 on end # I2C1 - device pci 15.2 on end # I2C2 - device pci 15.3 on end # I2C3 - device pci 16.0 on end # HECI1 - device pci 16.1 off end # HECI2 - device pci 16.2 off end # CSME - device pci 16.3 off end # CSME - device pci 16.4 off end # HECI3 - device pci 16.5 off end # HECI4 - device pci 17.0 on end # SATA - device pci 19.0 off end # I2C4 - device pci 19.1 on end # I2C5 - device pci 19.2 off end # UART2 - device pci 1c.0 on end # RP1 - device pci 1c.1 off end # RP2 - device pci 1c.2 off end # RP3 - device pci 1c.3 off end # RP4 - device pci 1c.4 on end # RP5 - device pci 1c.5 on end # RP6 - device pci 1c.6 off end # RP7 - device pci 1c.7 off end # RP8 - device pci 1d.0 on end # RP9 - device pci 1d.1 off end # RP10 - device pci 1d.2 on end # RP11 - device pci 1d.3 off end # RP12 - device pci 1e.0 on end # UART0 - device pci 1e.1 off end # UART1 - device pci 1e.2 on end # GSPI0 - device pci 1e.3 off end # GSPI1 - device pci 1f.0 on end # eSPI - device pci 1f.1 on end # P2SB - device pci 1f.2 hidden end # PMC - device pci 1f.3 on - chip drivers/intel/soundwire - device generic 0 on - chip drivers/soundwire/alc711 - # SoundWire Link 0 ID 1 - register "desc" = ""Headset Codec"" - device generic 0.1 on end - end - end - end - end # Intel Audio SNDW - device pci 1f.4 on end # SMBus - device pci 1f.5 on end # SPI - device pci 1f.6 off end # GbE - device pci 1f.7 off end # TH - end -end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c deleted file mode 100644 index d45bf8e067..0000000000 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/early_gpio.c +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include - -/* Early pad configuration in bootblock */ -static const struct pad_config early_gpio_table[] = { - /* WWAN_RST# */ - PAD_CFG_GPO(GPP_E10, 0, PLTRST), - /* WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_E13, 1, DEEP), -}; - -void variant_configure_early_gpio_pads(void) -{ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c deleted file mode 100644 index f91b94faf4..0000000000 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/gpio.c +++ /dev/null @@ -1,305 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -/* Pad configuration in ramstage*/ -static const struct pad_config gpio_table[] = { - /* SSD1_PWREN CPU SSD1 */ - PAD_CFG_GPO(GPP_D14, 1, PLTRST), - /* SSD1_RESET CPU SSD1 */ - PAD_CFG_GPO(GPP_F20, 1, PLTRST), - /* BT_RF_KILL_N */ - PAD_CFG_GPO(GPP_A13, 1, PLTRST), - /* WLAN RST# */ - PAD_CFG_GPO(GPP_H2, 1, PLTRST), - /* WIFI_WAKE_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_D13, NONE, DEEP, LEVEL, INVERT), - /* x4 PCIE slot1 PWREN */ - PAD_CFG_GPO(GPP_H17, 0, PLTRST), - /* x4 PCIE slot 1 RESET */ - PAD_CFG_GPO(GPP_F10, 1, PLTRST), - /* Retimer Force Power */ - PAD_CFG_GPO(GPP_E4, 0, PLTRST), - /* PEG Slot RST# */ - PAD_CFG_GPO(GPP_B2, 1, PLTRST), - /* M.2 SSD_2 Reset */ - PAD_CFG_GPO(GPP_H0, 1, PLTRST), - /* CAM1-IRQ */ - PAD_CFG_GPO(GPP_B23, 1, PLTRST), - /* CAM_STROBE */ - PAD_CFG_GPO(GPP_B18, 0, PLTRST), - /* Audio Codec INT N */ - PAD_CFG_GPI_APIC(GPP_H3, NONE, PLTRST, LEVEL, INVERT), - /* TCH PAD Power EN */ - PAD_CFG_GPO(GPP_F7, 1, PLTRST), - /* THC1 SPI2 RST# */ - PAD_CFG_GPO(GPP_F17, 1, PLTRST), - /* THC1_SPI2_INTB */ - PAD_CFG_GPI_APIC(GPP_F18, NONE, PLTRST, EDGE_SINGLE, INVERT), - /* THC1_SPI2_INTB */ - PAD_CFG_GPI(GPP_E17, NONE, PLTRST), - /* EC_SMI_N */ - PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, NONE), - /* EC_SLP_S0_CS_N */ - PAD_CFG_GPO(GPP_F9, 1, PLTRST), - /* WIFI RF KILL */ - PAD_CFG_GPO(GPP_E3, 1, PLTRST), - /* DISP_AUX_N_BIAS_GPIO */ - PAD_CFG_GPO(GPP_E23, 1, PLTRST), - /* WWAN WAKE N*/ - PAD_CFG_GPI_IRQ_WAKE(GPP_D18, NONE, DEEP, LEVEL, INVERT), - /* WWAN_DISABLE_N */ - PAD_CFG_GPO(GPP_D15, 1, PLTRST), - /* WWAN_RST# */ - PAD_CFG_GPO(GPP_E10, 1, PLTRST), - /* WWAN_PWR_EN */ - PAD_CFG_GPO(GPP_E13, 1, DEEP), - /* WWAN_PERST# */ - PAD_CFG_GPO(GPP_C5, 1, PLTRST), - /* PEG_SLOT_WAKE_N */ - PAD_CFG_GPI(GPP_A20, NONE, PLTRST), - /* UART_BT_WAKE_N */ - PAD_CFG_GPI_IRQ_WAKE(GPP_E0, NONE, DEEP, LEVEL, INVERT), - /* CAM CONN1 CLKEN */ - PAD_CFG_GPO(GPP_H15, 1, PLTRST), - /* CPU SSD2 PWREN */ - PAD_CFG_GPO(GPP_C2, 1, PLTRST), - /* CPU SSD2 RST# */ - PAD_CFG_GPO(GPP_H1, 1, PLTRST), - /* Sata direct Power */ - PAD_CFG_GPO(GPP_B4, 1, PLTRST), - /* M.2_PCH_SSD_PWREN */ - PAD_CFG_GPO(GPP_D16, 1, PLTRST), - - /* M.2_SSD_PDET_R */ - PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), - /* THC0 SPI1 CLK */ - PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), - /* THC0 SPI1 IO 1 */ - PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), - /* THC0 SPI1 IO 2 */ - PAD_CFG_NF(GPP_E1, NONE, DEEP, NF2), - /* THC0 SPI IO 3 */ - PAD_CFG_NF(GPP_E2, NONE, DEEP, NF2), - /* THC1 SPI1 RSTB */ - PAD_CFG_NF(GPP_E6, NONE, DEEP, NF2), - /* UART_RX(1) */ - PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), - /* UART_RX(2) */ - PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), - /* UART_RX(4) */ - PAD_CFG_NF(GPP_T4, NONE, DEEP, NF1), - /* UART_RX(5) */ - PAD_CFG_NF(GPP_T8, NONE, DEEP, NF1), - /* UART_RX(6) */ - PAD_CFG_NF(GPP_T12, NONE, DEEP, NF1), - - /* UART_TX(1) */ - PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), - /* UART_TX(2) */ - PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), - /* UART_TX(4) */ - PAD_CFG_NF(GPP_T5, NONE, DEEP, NF1), - /* UART_TX(5) */ - PAD_CFG_NF(GPP_T9, NONE, DEEP, NF1), - /* UART_TX(6) */ - PAD_CFG_NF(GPP_T13, NONE, DEEP, NF1), - - /* UART_RTS(1) */ - PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), - /* UART_RTS(2) */ - PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), - /* UART_RTS(4) */ - PAD_CFG_NF(GPP_T6, NONE, DEEP, NF1), - /* UART_RTS(5) */ - PAD_CFG_NF(GPP_T10, NONE, DEEP, NF1), - /* UART_RTS(6) */ - PAD_CFG_NF(GPP_T14, NONE, DEEP, NF1), - - /* UART_CTS(1) */ - PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), - /* UART_CTS(2) */ - PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), - /* UART_CTS(4) */ - PAD_CFG_NF(GPP_T7, NONE, DEEP, NF1), - /* UART_CTS(5) */ - PAD_CFG_NF(GPP_T11, NONE, DEEP, NF1), - /* UART_CTS(6) */ - PAD_CFG_NF(GPP_T15, NONE, DEEP, NF1), - - /* SPI_MOSI(1) */ - PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1), - /* SPI_MOSI(2) */ - PAD_CFG_NF(GPP_D12, NONE, DEEP, NF2), - - /* SPI_MIS0(0) */ - PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), - /* SPI_MIS0(1) */ - PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), - /* SPI_MIS0(2) */ - PAD_CFG_NF(GPP_D11, NONE, DEEP, NF2), - - /* SPI_CLK(0) */ - PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), - /* SPI_CLK(1) */ - PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), - /* SPI_CLK(2) */ - PAD_CFG_NF(GPP_D10, NONE, DEEP, NF2), - - /* SPI_CS(0, 0) */ - PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), - /* SPI_CS(0, 1) */ - PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), - /* SPI_CS(1, 0) */ - PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), - /* SPI_CS(2, 0) */ - PAD_CFG_NF(GPP_D9, NONE, DEEP, NF2), - - /* I2C_SCL(0) */ - PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), - /* I2C_SCL(1) */ - PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), - /* I2C_SCL(2) */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), - /* I2C_SCL(3) */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), - /* I2C_SCL(5) */ - PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), - /* I2C_SCL(6) */ - PAD_CFG_NF(GPP_T1, NONE, DEEP, NF1), - /* I2C_SCL(7) */ - PAD_CFG_NF(GPP_T3, NONE, DEEP, NF1), - - /* I2C_SDA(0) */ - PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), - /* I2C_SDA(1) */ - PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), - /* I2C_SDA(2) */ - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), - /* I2C_SDA(3) */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), - /* I2C_SDA(5) */ - PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), - /* I2C_SDA(6) */ - PAD_CFG_NF(GPP_T0, NONE, DEEP, NF1), - /* I2C_SDA(7) */ - PAD_CFG_NF(GPP_T2, NONE, DEEP, NF1), - - /* I2S0_SCLK */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), - /* I2S0_SFRM */ - PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), - /* I2S0_TXD */ - PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2), - /* I2S0_RXD */ - PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), - - /* I2S1_SCLK */ - PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), - /* I2S1_SFRM */ - PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), - /* I2S1_TXD */ - PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), - /* I2S1_RXD */ - PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), - - /* I2S2_SCLK */ - PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), - /* I2S2_SFRM */ - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - /* I2S2_TXD */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - /* I2S2_RXD */ - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), - - /* I2S_MCLK1_OUT */ - PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), - /* I2S_MCLK2_INOUT */ - PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), - - /* SNDW1_CLK */ - PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), - /* SNDW1_DATA */ - PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), - /* SNDW2_CLK */ - PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), - /* SNDW2_DATA */ - PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), - /* SNDW3_CLK */ - PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), - /* SNDW3_DATA */ - PAD_CFG_NF(GPP_S5, NONE, DEEP, NF2), - /* SNDW4_CLK */ - PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), - /* SNDW4_DATA */ - PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), - - /* SMB_CLK */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), - /* SMB_DATA */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), - - /* SATADevSlpPin to GPIO pin mapping */ - PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), - /* SATA DIRECT DEVSLP*/ - PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), - - /* SATA LED pin */ - PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), - - /* USB2 OC0 pins */ - PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), - /* USB2 OC1 pins */ - PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), - /* USB2 OC2 pins */ - PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), - /* USB2 OC3 pins */ - PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), - - /* GPIO pin for PCIE SRCCLKREQB */ - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), - - /* DDP1/2/3/4/A/B/C CTRLCLK and CTRLDATA pins */ - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A21, NONE, DEEP, NF2), - PAD_CFG_NF(GPP_A22, NONE, DEEP, NF2), - - /* HPD_1 (A19) and HPD_2 (A20) pins */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), - - /* IMGCLKOUT */ - PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), -}; - -void variant_configure_gpio_pads(void) -{ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} - -static const struct cros_gpio cros_gpios[] = { - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -}; - -const struct cros_gpio *variant_cros_gpios(size_t *num) -{ - *num = ARRAY_SIZE(cros_gpios); - return cros_gpios; -} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c b/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c deleted file mode 100644 index ec7ae88135..0000000000 --- a/src/mainboard/intel/adlrvp/variants/adlrvp_p/memory.c +++ /dev/null @@ -1,83 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include "../../board_id.h" -#include -#include - -static const struct mb_cfg ddr4_mem_config = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* Baseboard Rcomp target values */ - .rcomp_targets = {40, 30, 33, 33, 30}, - - .dq_pins_interleaved = true, - - .ect = true, /* Early Command Training */ - - .UserBd = BOARD_TYPE_MOBILE, -}; - -static const struct mb_cfg lpddr4_mem_config = { - /* DQ byte map */ - .dq_map = { - { 0, 2, 3, 1, 6, 7, 5, 4, /* Byte 0 */ - 10, 8, 11, 9, 14, 12, 13, 15 }, /* Byte 1 */ - { 12, 8, 14, 10, 11, 13, 15, 9, /* Byte 2 */ - 5, 0, 7, 3, 6, 2, 1, 4 }, /* Byte 3 */ - { 3, 0, 2, 1, 6, 5, 4, 7, /* Byte 4 */ - 12, 13, 14, 15, 10, 9, 8, 11 }, /* Byte 5 */ - { 2, 6, 7, 1, 3, 4, 0, 5, /* Byte 6 */ - 9, 13, 8, 15, 14, 11, 12, 10 }, /* Byte 7 */ - { 3, 0, 1, 2, 7, 4, 6, 5, /* Byte 0 */ - 10, 8, 11, 9, 14, 13, 12, 15 }, /* Byte 1 */ - { 10, 12, 14, 8, 9, 13, 15, 11, /* Byte 2 */ - 3, 7, 6, 2, 0, 4, 5, 1 }, /* Byte 3 */ - { 12, 15, 14, 13, 9, 10, 11, 8, /* Byte 4 */ - 7, 4, 6, 5, 0, 1, 3, 2 }, /* Byte 5 */ - { 0, 2, 4, 3, 1, 6, 7, 5, /* Byte 6 */ - 13, 9, 10, 11, 8, 12, 14, 15 }, /* Byte 7 */ - }, - - /* DQS CPU<>DRAM map */ - .dqs_map = { - /* Ch 0 1 2 3 */ - { 0, 1 }, { 1, 0 }, { 0, 1 }, { 0, 1 }, - { 0, 1 }, { 1, 0 }, { 1, 0 }, { 0, 1 } - }, - - .dq_pins_interleaved = false, - - .ect = true, /* Early Command Training */ - - .UserBd = BOARD_TYPE_MOBILE, -}; - -static const struct mb_cfg ddr5_mem_config = { - /* Baseboard uses only 100ohm Rcomp resistors */ - .rcomp_resistor = {100, 100, 100}, - - /* Baseboard Rcomp target values */ - .rcomp_targets = {50, 30, 30, 30, 27}, - - .dq_pins_interleaved = true, - - .ect = true, /* Early Command Training */ - - .UserBd = BOARD_TYPE_MOBILE, -}; - -const struct mb_cfg *variant_memory_params(void) -{ - int board_id = get_board_id(); - - if (board_id == ADL_P_LP4_1 || board_id == ADL_P_LP4_2) - return &lpddr4_mem_config; - else if (board_id == ADL_P_DDR4_1 || board_id == ADL_P_DDR4_2) - return &ddr4_mem_config; - else if (board_id == ADL_P_DDR5) - return &ddr5_mem_config; - - die("unsupported board id : 0x%x\n", board_id); -} diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb new file mode 100644 index 0000000000..e58e9fbdce --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb new file mode 100644 index 0000000000..e58e9fbdce --- /dev/null +++ b/src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb @@ -0,0 +1,4 @@ +chip soc/intel/alderlake + + device domain 0 on end +end diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h deleted file mode 100644 index 4303faf0d2..0000000000 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/ec.h +++ /dev/null @@ -1,73 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_EC_H__ -#define __BASEBOARD_EC_H__ - -#include -#include -#include - -#define MAINBOARD_EC_SCI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX)) - -#define MAINBOARD_EC_SMI_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)) - -/* EC can wake from S5 with lid or power button */ -#define MAINBOARD_EC_S5_WAKE_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON)) - -/* - * EC can wake from S3 with lid or power button or key press or - * mode change event. - */ -#define MAINBOARD_EC_S3_WAKE_EVENTS \ - (MAINBOARD_EC_S5_WAKE_EVENTS |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)) - -#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS) - -/* Log EC wake events plus EC shutdown events */ -#define MAINBOARD_EC_LOG_EVENTS \ - (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\ - EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC)) - -/* - * ACPI related definitions for ASL code. - */ - -/* Enable EC backed ALS device in ACPI */ -#define EC_ENABLE_ALS_DEVICE - -/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ -#define EC_ENABLE_SYNC_IRQ - -/* Enable EC backed PD MCU device in ACPI */ -#define EC_ENABLE_PD_MCU_DEVICE - -/* Enable LID switch and provide wake pin for EC */ -#define EC_ENABLE_LID_SWITCH -#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE - -#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */ -#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ -#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ - -#endif /* __BASEBOARD_EC_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h deleted file mode 100644 index b61276c0c1..0000000000 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/gpio.h +++ /dev/null @@ -1,18 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_GPIO_H__ -#define __BASEBOARD_GPIO_H__ - -#include -#include - -/* eSPI virtual wire reporting */ -#define EC_SCI_GPI GPE0_ESPI - -/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ -#define GPE_EC_WAKE GPE0_LAN_WAK - -/* EC sync IRQ */ -#define EC_SYNC_IRQ GPP_A15_IRQ - -#endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h deleted file mode 100644 index 537e62451a..0000000000 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ /dev/null @@ -1,31 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __BASEBOARD_VARIANTS_H__ -#define __BASEBOARD_VARIANTS_H__ - -#include -#include -#include -#include - -enum adl_boardid { - /* ADL-P LPDDR4 RVPs */ - ADL_P_LP4_1 = 0x10, - ADL_P_LP4_2 = 0x11, - /* ADL-P DDR5 RVPs */ - ADL_P_DDR5 = 0x12, - /* ADL-P DDR4 RVPs */ - ADL_P_DDR4_1 = 0x14, - ADL_P_DDR4_2 = 0x3F, -}; - -/* The next set of functions return the gpio table and fill in the number of - * entries for each table. */ -const struct cros_gpio *variant_cros_gpios(size_t *num); -/* Functions to configure GPIO as per variant schematics */ -void variant_configure_gpio_pads(void); -void variant_configure_early_gpio_pads(void); - -size_t variant_memory_sku(void); -const struct mb_cfg *variant_memory_params(void); -#endif /*__BASEBOARD_VARIANTS_H__ */ -- cgit v1.2.3