From 70296654825ddf5dfbe4980f385e8617c009a97e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 28 Oct 2020 13:50:19 +0530 Subject: mb/intel/adlrvp: Add support for DDR5 memory This patch adds DDR5 memory configuration parameters to FSP. TEST=Able to build and boot ADLRVP with DDR5 memory. Change-Id: I4711d66c7b4b7b09e15a4d06e28c876ec35bc192 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46485 Reviewed-by: Angel Pons Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- .../intel/adlrvp/variants/baseboard/include/baseboard/variants.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/intel/adlrvp/variants/baseboard') diff --git a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h index 005ec83a56..537e62451a 100644 --- a/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/variants/baseboard/include/baseboard/variants.h @@ -12,6 +12,8 @@ enum adl_boardid { /* ADL-P LPDDR4 RVPs */ ADL_P_LP4_1 = 0x10, ADL_P_LP4_2 = 0x11, + /* ADL-P DDR5 RVPs */ + ADL_P_DDR5 = 0x12, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, -- cgit v1.2.3