From 40f53f4b8790c72247901d05e4369ca3e04b28f8 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 20 Feb 2021 13:52:52 +0530 Subject: mb/intel/adlrvp: Add support for LP5 SKU with boardid 0x17 Change-Id: I4f17f9d58d2c07264d7d8e83a6fce832c9304c24 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/50980 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/romstage_fsp_params.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c') diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c index c95d469a7c..6ae5c17610 100644 --- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c @@ -57,7 +57,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) break; case ADL_P_LP4_1: case ADL_P_LP4_2: - case ADL_P_LP5: + case ADL_P_LP5_1: + case ADL_P_LP5_2: memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated); break; default: -- cgit v1.2.3