From 16e410669a369c4f09560cff99787e5439cd5e50 Mon Sep 17 00:00:00 2001
From: Subrata Banik <subrata.banik@intel.com>
Date: Tue, 6 Oct 2020 20:13:06 +0530
Subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code

List of changes:
1. Add DDR4 and LPDDR4 memory related code
- SPD for LPDDR4
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Fill FSP-M related UPD parameters
3. Add devicetree.cb config parameters related to FSP-M UPD

TEST=Able to build and boot ADL-P RVP till ramstage early

Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/mainboard/intel/adlrvp/romstage_fsp_params.c | 66 ++++++++++++++++++++++++
 1 file changed, 66 insertions(+)
 create mode 100644 src/mainboard/intel/adlrvp/romstage_fsp_params.c

(limited to 'src/mainboard/intel/adlrvp/romstage_fsp_params.c')

diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
new file mode 100644
index 0000000000..9d7cc9118f
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+#include <soc/meminit.h>
+#include <baseboard/variants.h>
+#include <cbfs.h>
+#include "board_id.h"
+
+#define SPD_ID_MASK 0x7
+
+static size_t get_spd_index(void)
+{
+	uint8_t board_id = get_board_id();
+	size_t spd_index;
+
+	printk(BIOS_INFO, "board id is 0x%x\n", board_id);
+
+	spd_index = board_id & SPD_ID_MASK;
+
+	printk(BIOS_INFO, "SPD index is 0x%x\n", (unsigned int)spd_index);
+	return spd_index;
+}
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	const struct mb_cfg *mem_config = variant_memory_params();
+	int board_id = get_board_id();
+	const bool half_populated = false;
+
+	const struct spd_info lpddr4_spd_info = {
+		.read_type = READ_SPD_CBFS,
+		.spd_spec.spd_index = get_spd_index(),
+	};
+
+	const struct spd_info ddr4_spd_info = {
+		.read_type = READ_SMBUS,
+		.spd_spec = {
+			.spd_smbus_address = {
+				[0] = 0xa0,
+				[1] = 0xa2,
+				[8] = 0xa4,
+				[9] = 0xa6,
+			},
+		},
+	};
+
+	switch (board_id) {
+	case ADL_P_DDR4_1:
+	case ADL_P_DDR4_2:
+		mupd->FspmConfig.DqPinsInterleaved = 1;
+		memcfg_init(&mupd->FspmConfig, mem_config, &ddr4_spd_info, half_populated);
+		break;
+	case ADL_P_LP4_1:
+	case ADL_P_LP4_2:
+		mupd->FspmConfig.DqPinsInterleaved = 0;
+		memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated);
+		break;
+	default:
+		die("Unknown board id = 0x%x\n", board_id);
+		break;
+	}
+}
-- 
cgit v1.2.3