From fb670fee3c8729a3b64f1fc171eb59073774029a Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Wed, 3 Feb 2021 15:10:50 +0530 Subject: mb/intel/adlrvp_m: Enable ADL_M RVP LP4 memory configuration List of changes: 1. Add board Ids for ADL-M LP4 configuration 2. Add spd hex files for LP4 configuration 3. Update memory.c file with correct Dq-dqs and byte mapping for LP4 BUG=None BRANCH=None TEST=Build and boot is successful for ADL M LP4 RVP Change-Id: Id817faee3fff2a8a911ebda35774dfb6ddc5524b Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/50257 Reviewed-by: Angel Pons Reviewed-by: Ronak Kanabar Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/intel/adlrvp/include/baseboard/variants.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/intel/adlrvp/include') diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 295e1b1e3b..8ecfa77b94 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -20,6 +20,8 @@ enum adl_boardid { /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, + /* ADL-M LP4 and LP5 RVPs */ + ADL_M_LP4 = 0x1, }; /* The next set of functions return the gpio table and fill in the number of -- cgit v1.2.3