From ae81d59ecaf050f7e14adb136560e993a98164cf Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Wed, 28 Oct 2020 22:28:07 +0530 Subject: mb/intel/adlrvp: Add support for LPDDR5 This patch adds LPDDR5 memory configuration parameters to FSP. TEST=Able to pass FSP-M MRC training on LPDDR5 RVP. Signed-off-by: Sridhar Siricilla Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: V Sowmya --- src/mainboard/intel/adlrvp/include/baseboard/variants.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/intel/adlrvp/include') diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 537e62451a..9cb8640860 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -14,6 +14,8 @@ enum adl_boardid { ADL_P_LP4_2 = 0x11, /* ADL-P DDR5 RVPs */ ADL_P_DDR5 = 0x12, + /* ADL-P LPDDR5 RVP */ + ADL_P_LP5 = 0x13, /* ADL-P DDR4 RVPs */ ADL_P_DDR4_1 = 0x14, ADL_P_DDR4_2 = 0x3F, -- cgit v1.2.3