From 351d3a1967ed73097f3517fc77872d67197c193e Mon Sep 17 00:00:00 2001 From: Krishna Prasad Bhat Date: Fri, 17 Dec 2021 16:08:04 +0530 Subject: mb/intel/adlrvp_n: Add support for ADL-N LP5 RVP Add support for Alder lake N LP5 RVP with board ID 0x7. Since SPD index 7 is unused earlier, ADL-N will use it. Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Signed-off-by: Krishna Prasad Bhat Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193 Tested-by: build bot (Jenkins) Reviewed-by: Kangheui Won Reviewed-by: Maulik V Vaghela --- src/mainboard/intel/adlrvp/include/baseboard/variants.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/intel/adlrvp/include') diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 9ab05f6bb1..143679ac56 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -24,6 +24,8 @@ enum adl_boardid { /* ADL-M LP4 and LP5 RVPs */ ADL_M_LP4 = 0x1, ADL_M_LP5 = 0x2, + /* ADL-N LP5 RVP */ + ADL_N_LP5 = 0x7, }; /* The next set of functions return the gpio table and fill in the number of -- cgit v1.2.3