From 2d22f82a0c3a23a023051126aedb65c57d3fce2f Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Wed, 3 Feb 2021 15:20:04 +0530 Subject: mb/intel/adlrvp_m: Enable ADL-M RVP LP5 memory configuration List of changes: 1. Add correct board Id for ADL-M LP5 configuration 2. Add spd hex files for LP5 Micron part 3. Update memory.c file with correct Dq-dqs and byte mapping for LP5 BUG=None BRANCH=None TEST=Build is successful for ADL-M RVP Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Ronak Kanabar --- src/mainboard/intel/adlrvp/include/baseboard/variants.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/intel/adlrvp/include') diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index 8ecfa77b94..af641488c9 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -22,6 +22,7 @@ enum adl_boardid { ADL_P_DDR4_2 = 0x3F, /* ADL-M LP4 and LP5 RVPs */ ADL_M_LP4 = 0x1, + ADL_M_LP5 = 0x2, }; /* The next set of functions return the gpio table and fill in the number of -- cgit v1.2.3