From 193203f90b49de06e4997aad53fb6d556c34798f Mon Sep 17 00:00:00 2001 From: Deepti Deshatty Date: Thu, 29 Apr 2021 21:32:58 +0530 Subject: mb/intel/adlrvp: Add board id for MR DDR5 SKU Add support for Maple Ridge DDR5 SKU with boardid 0x16 TEST=Verified build for ADL-P Chrome RVP Signed-off-by: Deepti Deshatty Change-Id: I9f0e9072f5866b60fb8463bb90f61915c78568db Reviewed-on: https://review.coreboot.org/c/coreboot/+/52760 Tested-by: build bot (Jenkins) Reviewed-by: Meera Ravindranath Reviewed-by: Maulik V Vaghela Reviewed-by: V Sowmya --- src/mainboard/intel/adlrvp/include/baseboard/variants.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/mainboard/intel/adlrvp/include') diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h index af641488c9..9a94db2c7a 100644 --- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h +++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h @@ -13,7 +13,8 @@ enum adl_boardid { ADL_P_LP4_1 = 0x10, ADL_P_LP4_2 = 0x11, /* ADL-P DDR5 RVPs */ - ADL_P_DDR5 = 0x12, + ADL_P_DDR5_1 = 0x12, + ADL_P_DDR5_2 = 0x16, /* ADL-P LPDDR5 RVP */ ADL_P_LP5_1 = 0x13, ADL_P_LP5_2 = 0x17, -- cgit v1.2.3