From 16e410669a369c4f09560cff99787e5439cd5e50 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 6 Oct 2020 20:13:06 +0530 Subject: mb/intel/adlrvp: Add ADL-P romstage mainboard code List of changes: 1. Add DDR4 and LPDDR4 memory related code - SPD for LPDDR4 - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Fill FSP-M related UPD parameters 3. Add devicetree.cb config parameters related to FSP-M UPD TEST=Able to build and boot ADL-P RVP till ramstage early Change-Id: Iffc5c17ed0725f61c8c274a80a1d27161ca6cebf Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46091 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/Kconfig | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/intel/adlrvp/Kconfig') diff --git a/src/mainboard/intel/adlrvp/Kconfig b/src/mainboard/intel/adlrvp/Kconfig index 27c3957b3e..97b4bf7a2b 100644 --- a/src/mainboard/intel/adlrvp/Kconfig +++ b/src/mainboard/intel/adlrvp/Kconfig @@ -12,6 +12,7 @@ config BOARD_SPECIFIC_OPTIONS select DRIVERS_USB_ACPI select DRIVERS_SPI_ACPI select SOC_INTEL_ALDERLAKE + select HAVE_SPD_IN_CBFS config CHROMEOS bool -- cgit v1.2.3