From efc40090f5711ea53df086606bf20ea8f476f871 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 5 Oct 2020 21:04:22 +0530 Subject: mb/intel/adlrvp: Add initial ADL-P mainboard code List of changes: 1. Initial code block to select SOC_INTEL_ALDERLAKE Kconfig 2. Add minimum code to make ADL-P RVP build successfully 3. Mainly bootblock and verstage code added to reach till verstage 4. Add support for 2 mainboards as ADL-P board with default EC (Windows SKU) and Chrome EC (Chrome SKU) 5. Add empty dsdt.asl to avoid compilation error TEST=Able to build and boot ADL-P RVP till romstage early. Change-Id: I2b551f48a4eb4d621d9a86c5d189c517d5610069 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/46054 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/Kconfig.name | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 src/mainboard/intel/adlrvp/Kconfig.name (limited to 'src/mainboard/intel/adlrvp/Kconfig.name') diff --git a/src/mainboard/intel/adlrvp/Kconfig.name b/src/mainboard/intel/adlrvp/Kconfig.name new file mode 100644 index 0000000000..0d54bb9a27 --- /dev/null +++ b/src/mainboard/intel/adlrvp/Kconfig.name @@ -0,0 +1,8 @@ +config BOARD_INTEL_ADLRVP_P + bool "Alderlake-P RVP" + select DRIVERS_UART_8250IO + select MAINBOARD_USES_IFD_EC_REGION + +config BOARD_INTEL_ADLRVP_P_EXT_EC + bool "Alderlake-P RVP with Chrome EC" + select INTEL_LPSS_UART_FOR_CONSOLE -- cgit v1.2.3