From 38f147ed3d9fdd6bfb23d7226f6fdd3fc5db53d0 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 8 Feb 2010 12:20:50 +0000 Subject: janitor task: unify and cleanup naming. cache_as_ram_auto.c and auto.c are both called "romstage.c" now. Signed-off-by: Stefan Reinauer Acked-by: Patrick Georgi git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/iei/juki-511p/auto.c | 63 ---------- src/mainboard/iei/juki-511p/romstage.c | 63 ++++++++++ src/mainboard/iei/nova4899r/auto.c | 58 --------- src/mainboard/iei/nova4899r/romstage.c | 58 +++++++++ src/mainboard/iei/pcisa-lx-800-r10/Makefile.inc | 6 +- .../iei/pcisa-lx-800-r10/cache_as_ram_auto.c | 137 --------------------- src/mainboard/iei/pcisa-lx-800-r10/romstage.c | 137 +++++++++++++++++++++ 7 files changed, 261 insertions(+), 261 deletions(-) delete mode 100644 src/mainboard/iei/juki-511p/auto.c create mode 100644 src/mainboard/iei/juki-511p/romstage.c delete mode 100644 src/mainboard/iei/nova4899r/auto.c create mode 100644 src/mainboard/iei/nova4899r/romstage.c delete mode 100644 src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c create mode 100644 src/mainboard/iei/pcisa-lx-800-r10/romstage.c (limited to 'src/mainboard/iei') diff --git a/src/mainboard/iei/juki-511p/auto.c b/src/mainboard/iei/juki-511p/auto.c deleted file mode 100644 index 655959fac4..0000000000 --- a/src/mainboard/iei/juki-511p/auto.c +++ /dev/null @@ -1,63 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Nikolay Petukhov - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#include -#include -#include -#include -#include -#include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -#include "superio/winbond/w83977f/w83977f_early_serial.c" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" -#include "cpu/x86/bist.h" -#include "pc80/udelay_io.c" - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) - -#include "northbridge/amd/gx1/raminit.c" - -static void main(unsigned long bist) -{ - /* Initialize the serial console. */ - w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure. */ - report_bist_failure(bist); - - /* Disable Watchdog Timer. */ - inb(0x043); - inb(0x843); - - cs5530_enable_rom(); - - /* Initialize RAM. */ - sdram_init(); - - /* Check RAM. */ - /* ram_check(0x00000000, 640 * 1024); */ -} diff --git a/src/mainboard/iei/juki-511p/romstage.c b/src/mainboard/iei/juki-511p/romstage.c new file mode 100644 index 0000000000..655959fac4 --- /dev/null +++ b/src/mainboard/iei/juki-511p/romstage.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "superio/winbond/w83977f/w83977f_early_serial.c" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "cpu/x86/bist.h" +#include "pc80/udelay_io.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1) + +#include "northbridge/amd/gx1/raminit.c" + +static void main(unsigned long bist) +{ + /* Initialize the serial console. */ + w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + /* Disable Watchdog Timer. */ + inb(0x043); + inb(0x843); + + cs5530_enable_rom(); + + /* Initialize RAM. */ + sdram_init(); + + /* Check RAM. */ + /* ram_check(0x00000000, 640 * 1024); */ +} diff --git a/src/mainboard/iei/nova4899r/auto.c b/src/mainboard/iei/nova4899r/auto.c deleted file mode 100644 index 0b15c3f40b..0000000000 --- a/src/mainboard/iei/nova4899r/auto.c +++ /dev/null @@ -1,58 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Luis Correia - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#include -#include -#include -#include -#include -#include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -#include "superio/winbond/w83977tf/w83977tf_early_serial.c" -#include "southbridge/amd/cs5530/cs5530_enable_rom.c" -#include "cpu/x86/bist.h" - -#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) - -#include "northbridge/amd/gx1/raminit.c" - -static void main(unsigned long bist) -{ - /* Initialize the serial console. */ - w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); - - /* Halt if there was a built in self test failure. */ - report_bist_failure(bist); - - cs5530_enable_rom(); - - /* Initialize RAM. */ - sdram_init(); - - /* Check RAM. */ - /* ram_check(0x00000000, 640 * 1024); */ -} diff --git a/src/mainboard/iei/nova4899r/romstage.c b/src/mainboard/iei/nova4899r/romstage.c new file mode 100644 index 0000000000..0b15c3f40b --- /dev/null +++ b/src/mainboard/iei/nova4899r/romstage.c @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Luis Correia + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "superio/winbond/w83977tf/w83977tf_early_serial.c" +#include "southbridge/amd/cs5530/cs5530_enable_rom.c" +#include "cpu/x86/bist.h" + +#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) + +#include "northbridge/amd/gx1/raminit.c" + +static void main(unsigned long bist) +{ + /* Initialize the serial console. */ + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + + cs5530_enable_rom(); + + /* Initialize RAM. */ + sdram_init(); + + /* Check RAM. */ + /* ram_check(0x00000000, 640 * 1024); */ +} diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Makefile.inc b/src/mainboard/iei/pcisa-lx-800-r10/Makefile.inc index f101f22d4e..0e4b263223 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Makefile.inc +++ b/src/mainboard/iei/pcisa-lx-800-r10/Makefile.inc @@ -12,7 +12,7 @@ crt0s += $(src)/cpu/x86/32bit/entry32.inc crt0s += $(src)/cpu/x86/16bit/reset16.inc crt0s += $(src)/arch/i386/lib/id.inc crt0s += $(src)/cpu/amd/model_lx/cache_as_ram.inc -crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc +crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc ldscripts := $(src)/arch/i386/init/ldscript_fallback_cbfs.lb ldscripts += $(src)/cpu/x86/16bit/entry16.lds @@ -22,8 +22,8 @@ ldscripts += $(src)/arch/i386/lib/failover.lds ifdef POST_EVALUATION -$(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/build.h - $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c -o $@ +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/build.h + $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c -S $(src)/mainboard/$(MAINBOARDDIR)/romstage.c -o $@ perl -e 's/\.rodata/.rom.data/g' -pi $@ perl -e 's/\.text/.section .rom.text/g' -pi $@ diff --git a/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c b/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c deleted file mode 100644 index 24a350b92b..0000000000 --- a/src/mainboard/iei/pcisa-lx-800-r10/cache_as_ram_auto.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define ASSEMBLY 1 -#define __PRE_RAM__ - -#include -#include -#include -#include -#include -#include "pc80/serial.c" -#include "arch/i386/lib/console.c" -#include "lib/ramtest.c" -#include "cpu/x86/bist.h" -#include "cpu/x86/msr.h" -#include -#include -#include "southbridge/amd/cs5536/cs5536.h" - -#define POST_CODE(x) outb(x, 0x80) -#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) - -#include "southbridge/amd/cs5536/cs5536_early_smbus.c" -#include "southbridge/amd/cs5536/cs5536_early_setup.c" -#include "superio/winbond/w83627hf/w83627hf_early_serial.c" - -static inline int spd_read_byte(unsigned int device, unsigned int address) -{ - return smbus_read_byte(device, address); -} - -#define ManualConf 1 /* Do automatic strapped PLL config */ -//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ -//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ -#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ -//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 -/* Hold Count - how long we will sit in reset */ -#define PLLMSRlo 0x00DE6000 - -#define DIMM0 0xA0 -#define DIMM1 0xA2 - -#include "northbridge/amd/lx/raminit.h" -#include "northbridge/amd/lx/pll_reset.c" -#include "northbridge/amd/lx/raminit.c" -#include "lib/generic_sdram.c" -#include "cpu/amd/model_lx/cpureginit.c" -#include "cpu/amd/model_lx/syspreinit.c" - -static void msr_init(void) -{ - msr_t msr; - - /* Setup access to the cache for under 1MB. */ - msr.hi = 0x24fffc02; - msr.lo = 0x1000A000; /* 0-A0000 write back */ - wrmsr(CPU_RCONF_DEFAULT, msr); - - msr.hi = 0x0; /* Write back */ - msr.lo = 0x0; - wrmsr(CPU_RCONF_A0_BF, msr); - wrmsr(CPU_RCONF_C0_DF, msr); - wrmsr(CPU_RCONF_E0_FF, msr); - - /* Setup access to the cache for under 640K. Note MC not setup yet. */ - msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU0 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU0 + 0x21, msr); - - msr.hi = 0x20000000; - msr.lo = 0xfff80; - wrmsr(MSR_GLIU1 + 0x20, msr); - - msr.hi = 0x20000000; - msr.lo = 0x80fffe0; - wrmsr(MSR_GLIU1 + 0x21, msr); -} - -static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup. */ -} - -void cache_as_ram_main(void) -{ - POST_CODE(0x01); - - static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} - }; - - SystemPreInit(); - msr_init(); - - cs5536_early_setup(); - - /* Note: must do this AFTER the early_setup! It is counting on some - * early MSR setup for CS5536. - */ - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - mb_gpio_init(); - uart_init(); - console_init(); - - pll_reset(ManualConf); - - cpuRegInit(); - - sdram_initialize(1, memctrl); - - /* ram_check(0, 640 * 1024); */ - - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ - return; -} diff --git a/src/mainboard/iei/pcisa-lx-800-r10/romstage.c b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c new file mode 100644 index 0000000000..24a350b92b --- /dev/null +++ b/src/mainboard/iei/pcisa-lx-800-r10/romstage.c @@ -0,0 +1,137 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define ASSEMBLY 1 +#define __PRE_RAM__ + +#include +#include +#include +#include +#include +#include "pc80/serial.c" +#include "arch/i386/lib/console.c" +#include "lib/ramtest.c" +#include "cpu/x86/bist.h" +#include "cpu/x86/msr.h" +#include +#include +#include "southbridge/amd/cs5536/cs5536.h" + +#define POST_CODE(x) outb(x, 0x80) +#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) + +#include "southbridge/amd/cs5536/cs5536_early_smbus.c" +#include "southbridge/amd/cs5536/cs5536_early_setup.c" +#include "superio/winbond/w83627hf/w83627hf_early_serial.c" + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#define ManualConf 1 /* Do automatic strapped PLL config */ +//#define PLLMSRhi 0x0000059C /* CPU and GLIU mult/div 500/400*/ +//#define PLLMSRhi 0x0000049C /* CPU and GLIU mult/div 500/333*/ +#define PLLMSRhi 0x0000039C /* CPU and GLIU mult/div 500/266*/ +//0x0000059C 0000 0000 0000 0000 0000 |0101 1|0|01 110|0 +/* Hold Count - how long we will sit in reset */ +#define PLLMSRlo 0x00DE6000 + +#define DIMM0 0xA0 +#define DIMM1 0xA2 + +#include "northbridge/amd/lx/raminit.h" +#include "northbridge/amd/lx/pll_reset.c" +#include "northbridge/amd/lx/raminit.c" +#include "lib/generic_sdram.c" +#include "cpu/amd/model_lx/cpureginit.c" +#include "cpu/amd/model_lx/syspreinit.c" + +static void msr_init(void) +{ + msr_t msr; + + /* Setup access to the cache for under 1MB. */ + msr.hi = 0x24fffc02; + msr.lo = 0x1000A000; /* 0-A0000 write back */ + wrmsr(CPU_RCONF_DEFAULT, msr); + + msr.hi = 0x0; /* Write back */ + msr.lo = 0x0; + wrmsr(CPU_RCONF_A0_BF, msr); + wrmsr(CPU_RCONF_C0_DF, msr); + wrmsr(CPU_RCONF_E0_FF, msr); + + /* Setup access to the cache for under 640K. Note MC not setup yet. */ + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU0 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU0 + 0x21, msr); + + msr.hi = 0x20000000; + msr.lo = 0xfff80; + wrmsr(MSR_GLIU1 + 0x20, msr); + + msr.hi = 0x20000000; + msr.lo = 0x80fffe0; + wrmsr(MSR_GLIU1 + 0x21, msr); +} + +static void mb_gpio_init(void) +{ + /* Early mainboard specific GPIO setup. */ +} + +void cache_as_ram_main(void) +{ + POST_CODE(0x01); + + static const struct mem_controller memctrl[] = { + {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + }; + + SystemPreInit(); + msr_init(); + + cs5536_early_setup(); + + /* Note: must do this AFTER the early_setup! It is counting on some + * early MSR setup for CS5536. + */ + w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + mb_gpio_init(); + uart_init(); + console_init(); + + pll_reset(ManualConf); + + cpuRegInit(); + + sdram_initialize(1, memctrl); + + /* ram_check(0, 640 * 1024); */ + + /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ + return; +} -- cgit v1.2.3