From 2ee5c9e21b6f2b3f7a76f27b90bd8f4b240839c7 Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Fri, 16 May 2008 18:08:54 +0000 Subject: Geode platforms that use a LPC Super I/O had the LPC serial IRQ set to all the possible IRQs generated by the SIO. This included IRQ 7 as the default parallel port IRQ. This overlapped with the MFGPT driver setting IRQ7 for it's own use. This fix removes IRQ7 from the serial IRQ list for all the mainboards that were setting it to prevent the conflict and crash when the MFGPT driver loads. Signed-off-by: Marc Jones Acked-by: Peter Stuge Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3329 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/iei/pcisa-lx-800-r10/Config.lb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/iei') diff --git a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb index 7c89aaffca..87aa03d741 100644 --- a/src/mainboard/iei/pcisa-lx-800-r10/Config.lb +++ b/src/mainboard/iei/pcisa-lx-800-r10/Config.lb @@ -78,8 +78,8 @@ chip northbridge/amd/lx # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power.... # Invert mask = IRQ 12 and 1 are active high. Keyboard and Mouse, UARTs, etc IRQs. OK - register "lpc_serirq_enable" = "0x000010da" - register "lpc_serirq_polarity" = "0x0000EF25" + register "lpc_serirq_enable" = "0x0000105a" + register "lpc_serirq_polarity" = "0x0000EFA5" register "lpc_serirq_mode" = "1" register "enable_gpio_int_route" = "0x0D0C0700" register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash -- cgit v1.2.3