From 91e9f676b779f3fc85efd0a5cac01a17cc66e01f Mon Sep 17 00:00:00 2001 From: Timothy Pearson Date: Thu, 19 Mar 2015 16:44:46 -0500 Subject: mainboards/amd/fam10: Add romstage timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Example output: 1:start of rom stage 542 2:before ram initialization 193,989 (193,447) 3:after ram initialization 3,319,114 (3,125,124) 4:end of romstage 3,320,004 (889) Change-Id: Idcde7dc4c7a1d6c3118c82b67e8c2fcd4a07553b Signed-off-by: Timothy Pearson Reviewed-on: http://review.coreboot.org/8776 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Paul Menzel Reviewed-by: Kyösti Mälkki --- src/mainboard/iei/kino-780am2-fam10/romstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) (limited to 'src/mainboard/iei/kino-780am2-fam10/romstage.c') diff --git a/src/mainboard/iei/kino-780am2-fam10/romstage.c b/src/mainboard/iei/kino-780am2-fam10/romstage.c index 991cd55602..5f99df6aad 100644 --- a/src/mainboard/iei/kino-780am2-fam10/romstage.c +++ b/src/mainboard/iei/kino-780am2-fam10/romstage.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #include #include @@ -77,6 +78,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 bsp_apicid = 0, val; msr_t msr; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -198,8 +202,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("Die Before MCT init."); + timestamp_add_now(TS_BEFORE_INITRAM); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); + timestamp_add_now(TS_AFTER_INITRAM); + cbmem_initialize_empty(); post_code(0x41); @@ -215,6 +222,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); + timestamp_add_now(TS_END_ROMSTAGE); + post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. -- cgit v1.2.3