From c583920a748fb8bd7999142433ad08641b06283d Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 12 Nov 2019 23:48:42 +0100 Subject: nb/intel/i945: Initialize console in bootblock Change-Id: Ic6ea158714998195614a63ee46a057f405de5616 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36796 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes --- src/mainboard/ibase/mb899/Makefile.inc | 2 + src/mainboard/ibase/mb899/early_init.c | 119 +++++++++++++++++++++++++++++++++ src/mainboard/ibase/mb899/romstage.c | 118 -------------------------------- 3 files changed, 121 insertions(+), 118 deletions(-) create mode 100644 src/mainboard/ibase/mb899/early_init.c delete mode 100644 src/mainboard/ibase/mb899/romstage.c (limited to 'src/mainboard/ibase') diff --git a/src/mainboard/ibase/mb899/Makefile.inc b/src/mainboard/ibase/mb899/Makefile.inc index 3f072f553f..992c3736a7 100644 --- a/src/mainboard/ibase/mb899/Makefile.inc +++ b/src/mainboard/ibase/mb899/Makefile.inc @@ -1,3 +1,5 @@ ramstage-y += superio_hwm.c ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c diff --git a/src/mainboard/ibase/mb899/early_init.c b/src/mainboard/ibase/mb899/early_init.c new file mode 100644 index 0000000000..ba8d30cf29 --- /dev/null +++ b/src/mainboard/ibase/mb899/early_init.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) +#define SUPERIO_DEV PNP_DEV(0x4e, 0) + +/* This box has one superio + * Also set up the GPIOs from the beginning. This is the "no schematic + * but safe anyways" method. + */ +void bootblock_mainboard_early_init(void) +{ + pnp_devfn_t dev; + + dev = SUPERIO_DEV; + pnp_enter_conf_state(dev); + + pnp_write_config(dev, 0x24, 0xc4); // PNPCVS + + pnp_write_config(dev, 0x29, 0x01); // GPIO settings + pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 + pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? + pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? + pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? + + dev = PNP_DEV(0x4e, W83627EHG_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 4); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x4e, W83627EHG_SP2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); + pnp_set_irq(dev, PNP_IDX_IRQ0, 3); + // pnp_write_config(dev, 0xf1, 4); // IRMODE0 + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); + pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); + //pnp_write_config(dev, 0xf0, 0x82); + pnp_set_enable(dev, 1); + + dev = PNP_DEV(0x4e, W83627EHG_GPIO2); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 1); // Just enable it + + dev = PNP_DEV(0x4e, W83627EHG_GPIO3); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output + pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 + pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient + + dev = PNP_DEV(0x4e, W83627EHG_FDC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + dev = PNP_DEV(0x4e, W83627EHG_PP); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + /* Enable HWM */ + dev = PNP_DEV(0x4e, W83627EHG_HWM); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} + +void mainboard_late_rcba_config(void) +{ + /* Set up virtual channel 0 */ + //RCBA32(0x0014) = 0x80000001; + + /* Device 1f interrupt pin register */ + RCBA32(D31IP) = 0x00042210; + /* Device 1d interrupt pin register */ + RCBA32(D28IP) = 0x00214321; + + /* dev irq route register */ + RCBA16(D31IR) = 0x0132; + RCBA16(D30IR) = 0x0146; + RCBA16(D29IR) = 0x0237; + RCBA16(D28IR) = 0x3201; + RCBA16(D27IR) = 0x0146; + + /* Enable PCIe Root Port Clock Gate */ + // RCBA32(0x341c) = 0x00000001; +} diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c deleted file mode 100644 index 2bc3cde103..0000000000 --- a/src/mainboard/ibase/mb899/romstage.c +++ /dev/null @@ -1,118 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include -#include -#include - -#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) -#define SUPERIO_DEV PNP_DEV(0x4e, 0) - -/* This box has one superio - * Also set up the GPIOs from the beginning. This is the "no schematic - * but safe anyways" method. - */ -void mainboard_superio_config(void) -{ - pnp_devfn_t dev; - - dev = SUPERIO_DEV; - pnp_enter_conf_state(dev); - - pnp_write_config(dev, 0x24, 0xc4); // PNPCVS - - pnp_write_config(dev, 0x29, 0x01); // GPIO settings - pnp_write_config(dev, 0x2a, 0x40); // GPIO settings should be fc but gets set to 02 - pnp_write_config(dev, 0x2b, 0xc0); // GPIO settings? - pnp_write_config(dev, 0x2c, 0x03); // GPIO settings? - pnp_write_config(dev, 0x2d, 0x20); // GPIO settings? - - dev = PNP_DEV(0x4e, W83627EHG_SP1); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 4); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627EHG_SP2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); - pnp_set_irq(dev, PNP_IDX_IRQ0, 3); - // pnp_write_config(dev, 0xf1, 4); // IRMODE0 - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627EHG_KBC); // Keyboard - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); - pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); - //pnp_write_config(dev, 0xf0, 0x82); - pnp_set_enable(dev, 1); - - dev = PNP_DEV(0x4e, W83627EHG_GPIO2); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 1); // Just enable it - - dev = PNP_DEV(0x4e, W83627EHG_GPIO3); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output - pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 - pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient - - dev = PNP_DEV(0x4e, W83627EHG_FDC); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - dev = PNP_DEV(0x4e, W83627EHG_PP); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - - /* Enable HWM */ - dev = PNP_DEV(0x4e, W83627EHG_HWM); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); - pnp_set_enable(dev, 1); - - pnp_exit_conf_state(dev); -} - -void mainboard_late_rcba_config(void) -{ - /* Set up virtual channel 0 */ - //RCBA32(0x0014) = 0x80000001; - - /* Device 1f interrupt pin register */ - RCBA32(D31IP) = 0x00042210; - /* Device 1d interrupt pin register */ - RCBA32(D28IP) = 0x00214321; - - /* dev irq route register */ - RCBA16(D31IR) = 0x0132; - RCBA16(D30IR) = 0x0146; - RCBA16(D29IR) = 0x0237; - RCBA16(D28IR) = 0x3201; - RCBA16(D27IR) = 0x0146; - - /* Enable PCIe Root Port Clock Gate */ - // RCBA32(0x341c) = 0x00000001; -} -- cgit v1.2.3