From 22d6ee8d9cda51d20ca4173593b9574f7dac65ff Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 10:03:40 +0100 Subject: nb/intel/i945: Hook up PCI domain and CPU bus ops to devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I4f30f5275d38c3eecf54d008b3edbf68071ab10d Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69294 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/ibase/mb899/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/ibase') diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 12104e4bb0..1b59fcc1b9 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -3,6 +3,7 @@ chip northbridge/intel/i945 register "gfx" = "GMA_STATIC_DISPLAYS(0)" device cpu_cluster 0 on + ops i945_cpu_bus_ops chip cpu/intel/socket_m device lapic 0 on end end @@ -11,6 +12,7 @@ chip northbridge/intel/i945 register "pci_mmio_size" = "768" device domain 0 on + ops i945_pci_domain_ops device pci 00.0 on end # host bridge device pci 01.0 off end # i945 PCIe root port device pci 02.0 on end # vga controller -- cgit v1.2.3