From b9d2589ca40026b543ecb5b008ce0d1bc346bf53 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 15 Jun 2018 22:02:28 +0200 Subject: mb/*/*: Harmonise FD and devicetree on boards featuring ICH7 On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/27122 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/ibase/mb899/devicetree.cb | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) (limited to 'src/mainboard/ibase/mb899') diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index c63e5d645f..3544c96739 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -45,17 +45,17 @@ chip northbridge/intel/i945 device pci 1c.0 on end # PCIe device pci 1c.1 on end # PCIe device pci 1c.2 on end # PCIe - #device pci 1c.3 off end # PCIe port 4 - #device pci 1c.4 off end # PCIe port 5 - #device pci 1c.5 off end # PCIe port 6 + device pci 1c.3 on end # PCIe port 4 + device pci 1c.4 on end # PCIe port 5 + device pci 1c.5 on end # PCIe port 6 device pci 1d.0 on end # USB UHCI device pci 1d.1 on end # USB UHCI device pci 1d.2 on end # USB UHCI device pci 1d.3 on end # USB UHCI device pci 1d.7 on end # USB2 EHCI device pci 1e.0 on end # PCI bridge - #device pci 1e.2 off end # AC'97 Audio - #device pci 1e.3 off end # AC'97 Modem + device pci 1e.2 on end # AC'97 Audio + device pci 1e.3 on end # AC'97 Modem device pci 1f.0 on # LPC bridge chip superio/winbond/w83627ehg device pnp 4e.0 off end # Floppy @@ -108,7 +108,6 @@ chip northbridge/intel/i945 device pci 1f.1 on end # IDE device pci 1f.2 on end # SATA device pci 1f.3 on end # SMBus - # device pci 1f.4 off end # Realtek ID Codec end # chip southbridge/intel/i82801gx end # device domain0 -- cgit v1.2.3